G11C 7 - Arrangements for writing information into, or reading information out from, a digital store

Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
12/2006
12/05/2006	US7145789 Low power low area precharge technique for a content addressable memory
12/05/2006	US7145374 Methods and apparatus for delay circuit
12/05/2006	CA2277717C Circuit and method for multiple match detection in content addressable memories
11/2006
11/30/2006	US20060272016 System and method for programming communication devices
11/30/2006	US20060271730 Method for initializing a Random Access Memory
11/30/2006	US20060271609 Semiconductor memory device having matrix of memory banks for multi-bit input/output function
11/30/2006	US20060268850 Data input circuit and semiconductor device utilizing data input circuit
11/30/2006	US20060268643 System and method for hidden-refresh rate modification
11/30/2006	US20060268642 Serial peripheral interface memory device with an accelerated parallel mode
11/30/2006	US20060268641 Method and apparatus for storing data in a write-once non-volatile memory
11/30/2006	US20060268640 Open digit line array architecture for a memory array
11/30/2006	US20060268639 Open digit line array architecture for a memory array
11/30/2006	US20060268638 Open digit line array architecture for a memory array
11/30/2006	US20060268632 Integrated circuit chip having a first delay circuit trimmed via a second delay circuit
11/30/2006	US20060268631 RFID device having nonvolatile ferroelectric memory device
11/30/2006	US20060268630 Semiconductor memory device having sense amp over-driving structure and method of over-driving sense amplifier thereof
11/30/2006	US20060268627 Semiconductor storage device
11/30/2006	US20060268626 Memory with dynamically adjustable supply
11/30/2006	US20060268625 Semiconductor integrated circuit and microcomputer
11/30/2006	US20060268624 Semiconductor memory device and data write and read method thereof
11/30/2006	US20060268623 Transmitting/receiving apparatus and method in a closed-loop MIMO system
11/30/2006	US20060268621 Method for programming a reference cell
11/30/2006	US20060268610 Nonvolatile memory system, semiconductor memory, and writing method
11/30/2006	US20060267077 Semiconductor memory element, semiconductor memory device and method of fabricating the same
11/30/2006	DE102005025166A1 Verfahren zum Anpassen von Schaltungskomponenten eines Speichermoduls und Speichermodul A method of adapting circuit components of a memory module and memory module
11/29/2006	EP1727147A1 Sense amplifier for dynamic memory
11/29/2006	EP1726016A1 Technique for efficient video re-sampling
11/29/2006	CN2842659Y Flash memory protective circuit
11/29/2006	CN1871663A Semiconductor storage device and method for refreshing the same
11/29/2006	CN1870176A Page buffer circuit, flash memory device and program operation method of the flash memory device
11/29/2006	CN1870172A Method and apparatus for adapting circuit components of a memory module to changing operating conditions
11/29/2006	CN1868557A 数字音乐电治疗仪 Digital music electrical therapy device
11/29/2006	CN1287525C Topology for providing clock signal and multi-path unit on electric circuit module
11/29/2006	CN1287443C Method for semiconductor memory device to produce initializing signal
11/29/2006	CN1287250C Method and system for writing data to memory
11/28/2006	US7143331 Error correction apparatus for performing consecutive reading of multiple code words
11/28/2006	US7143303 Memory device for compensating for a clock skew causing a centering error and a method for compensating for the clock skew
11/28/2006	US7143230 Processor system using synchronous dynamic memory
11/28/2006	US7143201 Externally accessible playback apparatus and method
11/28/2006	US7142543 High speed programmable counter
11/28/2006	US7142479 Addressing data within dynamic random access memory
11/28/2006	US7142476 Refresh counter circuit and control method for refresh operation
11/28/2006	US7142475 Memory device having a configurable oscillator for refresh operation
11/28/2006	US7142474 Magnetic memory device and recording control method for magnetic memory device
11/28/2006	US7142473 Semiconductor device having semiconductor memory with sense amplifier
11/28/2006	US7142470 Methods and systems for generating latch clock used in memory reading
11/28/2006	US7142469 Circuit for controlling an enabling time of an internal control signal according to an operating frequency of a memory device and the method thereof
11/28/2006	US7142468 Control method of semiconductor memory device and semiconductor memory device
11/28/2006	US7142467 Synchronous semiconductor memory device
11/28/2006	US7142466 Determining optimal time instances to sense the output of a memory array which can generate data outputs with variable delay
11/28/2006	US7142465 Semiconductor memory
11/28/2006	US7142464 Apparatus and methods for multi-level sensing in a memory array
11/28/2006	US7142463 Register file method incorporating read-after-write blocking using detection cells
11/28/2006	US7142462 Input signal receiving device of semiconductor memory unit
11/28/2006	US7142461 Active termination control though on module register
11/28/2006	US7142457 Non-volatile semiconductor memory device
11/28/2006	US7142456 Distributed programmed memory cells used as memory reference currents
11/28/2006	US7142450 Programmable sub-surface aggregating metallization structure and method of making same
11/28/2006	US7142445 Ferroelectric memory device, method of driving the same, and driver circuit
11/28/2006	US7142444 Data reading method, data writing method, and semiconductor memory device
11/28/2006	US7142443 Reduced data line pre-fetch scheme
11/28/2006	US7142442 Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability
11/28/2006	US7142022 Clock enable buffer for entry of self-refresh mode
11/28/2006	US7142021 Data inversion circuits having a bypass mode of operation and methods of operating the same
11/23/2006	WO2006124571A2 Baselining amplification data
11/23/2006	WO2006124376A1 Measure-initialized delay locked loop with live measurement
11/23/2006	WO2006124300A1 Identical chips with different operations in a system
11/23/2006	WO2006122932A1 Method to handle write mask in dram memory
11/23/2006	US20060265622 Synchronization devices having input/output delay model tuning elements
11/23/2006	US20060265621 Apparatus and method for generating a delayed clock signal
11/23/2006	US20060265620 Apparatus and method for generating a delayed clock signal
11/23/2006	US20060265619 Apparatus and method for generating a delayed clock signal
11/23/2006	US20060265618 Apparatus and method for generating a delayed clock signal
11/23/2006	US20060265598 Access to a computing environment by computing devices
11/23/2006	US20060265565 Dual edge command
11/23/2006	US20060265564 Software command sequence for optimized power consumption
11/23/2006	US20060262629 Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell
11/23/2006	US20060262625 Semiconductor device
11/23/2006	US20060262624 Method and architecture to calibrate read operatons in synchronous flash memory
11/23/2006	US20060262623 Phase locked loop with temperature compensation
11/23/2006	US20060262622 Swtiched capacitor DRAM sense amplifier with immunity to mismatch and offsets
11/23/2006	US20060262621 Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets
11/23/2006	US20060262620 Serially sensing the output of multilevel cell arrays
11/23/2006	US20060262619 Sense amplifier circuit and method for a DRAM
11/23/2006	US20060262618 Semiconductor device and testing method thereof
11/23/2006	US20060262617 Page access circuit of semiconductor memory device
11/23/2006	US20060262616 Method and apparatus for implementing high speed memory
11/23/2006	US20060262613 Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted
11/23/2006	US20060262612 Method of operating a memory cell
11/23/2006	US20060262611 Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods
11/23/2006	US20060262609 Non-volatile semiconductor memory device and semiconductor disk device
11/23/2006	US20060262608 Performing multiple read operations via a single read command
11/23/2006	US20060262587 Memory module and memory system
11/23/2006	US20060262585 Active shielding for a circuit comprising magnetically sensitive materials
11/23/2006	US20060262584 Computer Memory Cards Using Flash EEprom Integrated Circuit Chips and Memory-Controller Systems
11/23/2006	US20060261448 High permeability composite films to reduce noise in high speed interconnects
11/23/2006	US20060261438 Capacitive techniques to reduce noise in high speed interconnections
11/23/2006	DE102005022763A1 Electronic circuit, circuit arrangement and production process with multi-gate functional FET and protective FET having a charge-reducing transistor and a low trigger voltage
11/23/2006	DE10154613B4 Verfahren zum Vorladen von Speicherzellen eines dynamischen Halbleiterspeichers beim Power Up sowie Halbleiterspeicher Method of precharging memory cells of a dynamic semiconductor memory during power-up as well as semiconductor memory
11/22/2006	EP1724787A2 Apparatus and method for updating data in a dual port memory

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