| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 02/01/2000 | US6021070 Circuit and method for reading and writing data in a memory device |
| 02/01/2000 | US6021065 Spin dependent tunneling memory |
| 02/01/2000 | US6021064 Layout for data storage circuit using shared bit line and method therefor |
| 02/01/2000 | US6021063 Method and structure for improving data retention in a DRAM |
| 02/01/2000 | US6021062 Semiconductor memory device capable of reducing a load imposed upon a sense amplifier to shorten a sensing time |
| 02/01/2000 | US6021061 Semiconductor memory device |
| 02/01/2000 | US6020781 Step-up circuit using two frequencies |
| 02/01/2000 | US6020780 Substrate potential control circuit capable of making a substrate potential change in response to a power-supply voltage |
| 02/01/2000 | US6020763 High speed decoder without race condition |
| 02/01/2000 | US6020761 Input buffers and controlling methods for integrated circuit memory devices that operate with low voltage transistor-transistor logic (LVTTL) and with stub series terminated transceiver logic (SSTL) |
| 02/01/2000 | US6019501 Address generating device for memory tester |
| 01/27/2000 | WO2000004592A1 Fabricating an mtj with low areal resistance |
| 01/27/2000 | WO2000004591A1 Low resistance magnetic tunneling junction |
| 01/27/2000 | WO2000004555A2 Storage cell system in which an electric resistance of a storage element represents an information unit and can be influenced by a magnetic field, and method for producing same |
| 01/27/2000 | WO2000004552A1 Low switching field magnetic tunneling junction usable for multi-state magnetic memory cell |
| 01/27/2000 | WO2000004551A1 Mram with shared word and digit lines |
| 01/27/2000 | WO2000004481A2 An apparatus and method for thermal regulation in memory subsystems |
| 01/27/2000 | WO1999063542B1 Radiation hardened six transistor random access memory and memory device |
| 01/27/2000 | DE19933894A1 Semiconductor memory and the process used to handle fault conditions uses redundance selection lines coupled to the address decoder and a shift redundance circuit |
| 01/27/2000 | DE19928454A1 Solid state memory that uses a series decoder circuit coupled to a series address register that is used to apply selection signals to the memory blocks |
| 01/27/2000 | DE19832994A1 Ferroelectric memory arrangement |
| 01/26/2000 | EP0974978A1 Semiconductor memory device capable of performing a write operation 1 or 2 cycles after receiving a write command without a dead cycle |
| 01/26/2000 | EP0974977A2 Integrated memory |
| 01/26/2000 | EP0974097A1 Method and apparatus for combining a volatile and a nonvolatile memory array |
| 01/26/2000 | EP0617363B1 Defective cell substitution in EEprom array |
| 01/26/2000 | CN1242606A Magnetic random access memory (MRAM) array with magnetic tunnel junction (MTJ) cells and remote diodes |
| 01/26/2000 | CN1242578A Switchable multi bit semiconductor memory device |
| 01/25/2000 | USRE36531 Semiconductor memory device including memory cells connected to a ground line |
| 01/25/2000 | US6018811 Layout for semiconductor memory device wherein intercoupling lines are shared by two sets of fuse banks and two sets of redundant elements not simultaneously active |
| 01/25/2000 | US6018492 Semiconductor memory device |
| 01/25/2000 | US6018491 Synchronous dynamic random access memory |
| 01/25/2000 | US6018487 Read-only memory device having bit line discharge circuitry and method of reading data from the same |
| 01/25/2000 | US6018486 Reading method and circuit for dynamic memory |
| 01/25/2000 | US6018484 Method and apparatus for testing random access memory devices |
| 01/25/2000 | US6018483 Distributed block redundancy for memory devices |
| 01/25/2000 | US6018481 Dynamic semiconductor memory device |
| 01/25/2000 | US6018480 Method and system which permits logic signal routing over on-chip memories |
| 01/25/2000 | US6018478 Random access memory with separate row and column designation circuits for reading and writing |
| 01/25/2000 | US6018477 Intelligent refreshing method and apparatus for increasing multi-level non-volatile memory charge retention reliability |
| 01/25/2000 | US6018354 Method for accessing banks of DRAM |
| 01/25/2000 | US6018259 Phase locked delay circuit |
| 01/25/2000 | US6018253 Register with current-steering input network |
| 01/25/2000 | US6018177 DRAM cell and array to store two-bit data |
| 01/25/2000 | US6018172 Semiconductor memory device including memory cell transistors formed on SOI substrate and having fixed body regions |
| 01/25/2000 | US6018171 Shallow junction ferroelectric memory cell having a laterally extending p-n junction and method of making the same |
| 01/20/2000 | WO2000003397A1 Integrated circuit |
| 01/20/2000 | WO2000003396A2 Ferroelectric read/write memory having series-connected storage cells (cfram) |
| 01/20/2000 | WO2000003395A1 Ferroelectric ram arrangement |
| 01/20/2000 | WO2000003258A1 Integrated circuit with improved synchronism for an external clock signal at a data output |
| 01/20/2000 | DE19926588A1 Low skew pulse generator for double data rate synchronous DRAM |
| 01/20/2000 | DE19904542A1 Multi-bit dynamic random-access memory e.g. for personal computer is switched between binary memory mode and multi-value memory mode in response to mode selection signal fed to mode register |
| 01/20/2000 | DE19902280A1 Halbleiter-Speicherbauelement und Verfahren zum Auffrischen eines Halbleiter-Speicherbauelements A semiconductor memory device and method for refreshing of a semiconductor memory device |
| 01/19/2000 | EP0973169A2 Element exploiting magnetic material and addressing method therefor |
| 01/19/2000 | EP0973167A2 High-speed cycle clock-synchronous memory device |
| 01/19/2000 | EP0972287A1 High-efficiency miniature magnetic integrated circuit structures |
| 01/19/2000 | EP0972284A1 Electric or electronic component and application as non volatile memory and device with surface acoustic waves |
| 01/19/2000 | EP0972270A1 A storage apparatus and writing and/or reading methods for use in hierarchical coding |
| 01/19/2000 | CN1242088A Method and apparatus for correcting a multilevel cell memory by using error locating codes |
| 01/19/2000 | CN1241785A Semiconductor memory device and data read method thereof |
| 01/19/2000 | CN1241784A 半导体存储器 Semiconductor memory |
| 01/19/2000 | CN1241783A Semiconductor memory device |
| 01/19/2000 | CN1241753A Semiconductor integrated circuit and data processing system |
| 01/18/2000 | US6016534 Data processing system for controlling operation of a sense amplifier in a cache |
| 01/18/2000 | US6016284 Address transition detector for memory device |
| 01/18/2000 | US6016283 Multiple data rate synchronous DRAM for enhancing data transfer speed |
| 01/18/2000 | US6016281 Memory with word line voltage control |
| 01/18/2000 | US6016280 Semiconductor integrated circuit device |
| 01/18/2000 | US6016277 Reference voltage generator for reading a ROM cell in an integrated RAM/ROM memory device |
| 01/18/2000 | US6016276 Semiconductor memory device which can be set one from multiple threshold value |
| 01/18/2000 | US6016271 Method and circuit for generating a gate voltage in non-volatile memory devices |
| 01/18/2000 | US6016269 Quantum random address memory with magnetic readout and/or nano-memory elements |
| 01/18/2000 | US6016268 Three transistor multi-state dynamic memory cell for embedded CMOS logic applications |
| 01/18/2000 | US6016267 High speed, high bandwidth, high density, nonvolatile memory system |
| 01/18/2000 | US6016266 Semiconductor device with a ferroelectric capacitor |
| 01/18/2000 | US6016068 Power on reset circuit capable of generating power on reset signal without fail |
| 01/18/2000 | US6016065 Charges recycling differential logic(CRDL) circuit and storage elements and devices using the same |
| 01/18/2000 | US6015738 Method for fabricating transistorless, multistable current-mode memory cells and memory arrays |
| 01/13/2000 | WO1999062068A3 Magnetic memory |
| 01/13/2000 | DE19929121A1 Buffer arrangement for improved loading of data onto a busline |
| 01/13/2000 | DE19830571A1 Integrierte Schaltung Integrated circuit |
| 01/13/2000 | DE19830111A1 Integrierter Speicher Built-in Memory |
| 01/12/2000 | EP0971424A2 Spin-valve structure and method for making spin-valve structures |
| 01/12/2000 | EP0971423A1 Spin-valve structure and method for making same |
| 01/12/2000 | EP0971361A1 High data rate write process for non-volatile flash memories |
| 01/12/2000 | EP0971360A1 Semiconductor memory cell |
| 01/12/2000 | EP0970516A1 Strontium bismuth niobate tantalate ferroelectric thin film |
| 01/12/2000 | CN1241002A Interleaved sense amplifier with single-sided precharge device |
| 01/12/2000 | CN1241000A Fuse circuit and redundant decoder |
| 01/11/2000 | USRE36490 Power and signal line bussing method for memory devices |
| 01/11/2000 | US6014509 Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells |
| 01/11/2000 | US6014341 Synchronous-type semiconductor storage |
| 01/11/2000 | US6014340 Synchronous semiconductor memory device having internal circuitry enabled only when commands are applied in normal sequence |
| 01/11/2000 | US6014339 Synchronous DRAM whose power consumption is minimized |
| 01/11/2000 | US6014337 Semiconductor storage device |
| 01/11/2000 | US6014335 Semiconductor memory device |
| 01/11/2000 | US6014333 Semiconductive memory device capable of carrying out a write-in operation at a high speed |
| 01/11/2000 | US6014330 Non-volatile semiconductor memory device |
| 01/11/2000 | US6014327 Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell |
| 01/11/2000 | CA2039496C Information transfer method, information transfer apparatus, and its driving method |
| 01/06/2000 | WO2000000983A1 Techniques for analog and multilevel storage using integrated circuit technology |