| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
|---|
| 03/14/2000 | US6038158 Semiconductor memory |
| 03/14/2000 | US6037815 Pulse generating circuit having address transition detecting circuit |
| 03/14/2000 | US6037813 Semiconductor device capable of selecting operation mode based on clock frequency |
| 03/14/2000 | US6037799 Circuit and method for selecting a signal |
| 03/14/2000 | US6037792 Burn-in stress test mode |
| 03/09/2000 | WO2000013184A1 Block write circuit and method for wide data path memory devices |
| 03/09/2000 | DE19912967A1 Verzögerungsregelkreisschaltung und Steuerverfahren hierfür Delay locked loop circuit and control method therefor |
| 03/09/2000 | DE19903197A1 Integrated memory with segmented word line |
| 03/08/2000 | EP0984360A2 Bus signal line driver |
| 03/08/2000 | EP0983593A2 Semi-conductor device with a memory cell |
| 03/08/2000 | CN1246710A Integrated circuit device with sychronous signal generator |
| 03/08/2000 | CN1246709A Storage structure in ferroelectric nonvolatile memory and its read method |
| 03/08/2000 | CN1246708A Magnetic memory cell with off-axis reference layer oriented for improving response |
| 03/07/2000 | US6035427 Convolutional interleaver and method for generating memory address therefor |
| 03/07/2000 | US6035381 Memory device including main memory storage and distinct key storage accessed using only a row address |
| 03/07/2000 | US6035370 Method for modifying signals received by memory cards RAS signals as address lines |
| 03/07/2000 | US6035369 Method and apparatus for providing a memory with write enable information |
| 03/07/2000 | US6035365 Dual clocked synchronous memory device having a delay time register and method of operating same |
| 03/07/2000 | US6034919 Method and apparatus for using extended-data output memory devices in a system designed for fast page mode memory devices |
| 03/07/2000 | US6034918 Method of operating a memory having a variable data output length and a programmable register |
| 03/07/2000 | US6034917 Control circuit for terminating a memory access cycle in a memory block of an electronic storage device |
| 03/07/2000 | US6034916 Data masking circuits and methods for integrated circuit memory devices, including data strobe signal synchronization |
| 03/07/2000 | US6034913 Apparatus and method for high-speed wordline driving with low area overhead |
| 03/07/2000 | US6034911 Semiconductor memory device for a rapid random access |
| 03/07/2000 | US6034909 Method and apparatus for bit line isolation for random access memory devices |
| 03/07/2000 | US6034904 Semiconductor memory device having selection circuit for arbitrarily setting a word line to selected state at high speed in test mode |
| 03/07/2000 | US6034903 Semiconductor memory device with identification fuse |
| 03/07/2000 | US6034901 Clock control circuit |
| 03/07/2000 | US6034900 Memory device having a relatively wide data bus |
| 03/07/2000 | US6034899 Memory cell of nonvolatile semiconductor memory device |
| 03/07/2000 | US6034894 Nonvolatile semiconductor storage device having buried electrode within shallow trench |
| 03/07/2000 | US6034892 Nonvolatile memory cell and method for programming and/or verifying the same |
| 03/07/2000 | US6034888 Reading circuit for nonvolatile analog memories, in particular flash-eeprom memories, with direct and constant current threshold voltage reading |
| 03/07/2000 | US6034887 Non-volatile magnetic memory cell and devices |
| 03/07/2000 | US6034885 Multilevel memory cell sense amplifier system and sensing methods |
| 03/07/2000 | US6034884 Nonvolatile dynamic random access memory with ferroelectric capacitors |
| 03/07/2000 | US6034882 Vertically stacked field programmable nonvolatile memory and method of fabrication |
| 03/07/2000 | US6034878 Source-clock-synchronized memory system and memory unit |
| 03/07/2000 | US6034567 Semiconductor integrated circuit device provided with a differential amplifier |
| 03/07/2000 | US6034563 Semiconductor integrated circuit having reduced current leakage and high speed |
| 03/07/2000 | US6034391 Semiconductor device including capacitance element having high area efficiency |
| 03/07/2000 | US6034387 Methods of operating ferroelectric memory devices having linear reference cells therein |
| 03/02/2000 | WO2000011676A1 An embedded dram architecture with local data drivers and programmable number of data read and data write lines |
| 03/02/2000 | WO2000011675A1 Method and apparatus to control the temperature of a component |
| 03/02/2000 | WO2000011674A1 Method and apparatus for built-in self test of integrated circuits |
| 03/02/2000 | DE19919578A1 Synchronous semiconducting memory has control circuit that can exert control according to external control signal so only data corresponding to address can be read out of/written into memory cell |
| 03/02/2000 | DE19909671A1 Halbleiterspeicherbauelement The semiconductor memory device |
| 03/02/2000 | DE19903600A1 Ferroelectric random-access semiconductor memory |
| 03/01/2000 | EP0982779A2 Memory structure in ferroelectric nonvolatile memory and readout method therefor |
| 03/01/2000 | EP0982777A1 Wordline driver circuit using ring-shaped devices |
| 03/01/2000 | EP0982736A2 Magnetic memory |
| 03/01/2000 | EP0982735A2 Method and apparatus for bit line recovery in dynamic random access memory |
| 03/01/2000 | CN1246198A 半导体集成电路器件 The semiconductor integrated circuit device |
| 03/01/2000 | CN1245958A Synchronized semiconductor memory |
| 02/29/2000 | US6032248 Microcontroller including a single memory module having a data memory sector and a code memory sector and supporting simultaneous read/write access to both sectors |
| 02/29/2000 | US6032229 Semiconductor memory device and information processor using the same |
| 02/29/2000 | US6032222 Semiconductor memory device with simultaneously write capability |
| 02/29/2000 | US6032215 Synchronous memory device utilizing two external clocks |
| 02/29/2000 | US6032214 Method of operating a synchronous memory device having a variable data output length |
| 02/29/2000 | US6031788 Semiconductor integrated circuit |
| 02/29/2000 | US6031786 Operation control circuits and methods for integrated circuit memory devices |
| 02/29/2000 | US6031785 Random access memory having burst mode capability and method for operating the same |
| 02/29/2000 | US6031782 Semiconductor memory device provided with an interface circuit consuming a reduced amount of current consumption |
| 02/29/2000 | US6031781 Semiconductor memory device allowing high-speed activation of internal circuit |
| 02/29/2000 | US6031780 Semiconductor memory device |
| 02/29/2000 | US6031779 Dynamic memory |
| 02/29/2000 | US6031778 Semiconductor integrated circuit |
| 02/29/2000 | US6031773 Method for stress testing the memory cell oxide of a DRAM capacitor |
| 02/29/2000 | US6031769 Data reading circuit for semiconductor memory device |
| 02/29/2000 | US6031768 Self boosted wordline |
| 02/29/2000 | US6031758 Semiconductor memory device having faulty cells |
| 02/29/2000 | US6031755 Non-volatile semiconductor memory device and its testing method |
| 02/29/2000 | US6031754 Ferroelectric memory with increased switching voltage |
| 02/29/2000 | US6031753 Nonvolatile ferroelectric memory and circuit for controlling the same |
| 02/29/2000 | US6031397 Negative voltage detection circuit offsetting fluctuation of detection level |
| 02/29/2000 | US6031273 All-metal, giant magnetoresistive, solid-state component |
| 02/29/2000 | US6030871 Process for producing two bit ROM cell utilizing angled implant |
| 02/29/2000 | US6030865 Process for manufacturing semiconductor integrated circuit device |
| 02/24/2000 | WO2000010252A1 Ddl circuit adjustable with external load |
| 02/24/2000 | WO2000010178A1 Magnetoresistive element and the use thereof as storage element in a storage cell array |
| 02/24/2000 | WO2000010172A2 Storage cell array and corresponding production method |
| 02/24/2000 | WO2000010171A1 On-chip word line voltage generation for dram embedded in logic process |
| 02/24/2000 | WO2000010024A1 Device comprising a first and a second ferromagnetic layer separated by a non-magnetic spacer layer |
| 02/24/2000 | WO2000010023A1 Magnetic field sensor comprising a spin tunneling junction element |
| 02/24/2000 | WO2000010022A1 Magnetic field sensor with perpendicular to layer sensitivity, comprising a giant magnetoresistance material or a spin tunnel junction |
| 02/24/2000 | WO2000003396A3 Ferroelectric read/write memory having series-connected storage cells (cfram) |
| 02/24/2000 | DE19937829A1 Data input-output circuit for integrated circuit devices e.g. memory devices has a number of output units and a control unit |
| 02/24/2000 | DE19836567A1 Memory cell structure with magneto-resistive memory elements comprises a magnetizable yoke surrounding one of the intersecting lines at a memory element location |
| 02/24/2000 | DE19832991A1 Speicheranordnung aus einer Vielzahl von resistiven ferroelektrischen Speicherzellen Memory arrangement comprising a multiplicity of resistive ferroelectric memory cells |
| 02/23/2000 | EP0846325B1 Reduced area sense amplifier isolation layout in a dynamic ram architecture |
| 02/23/2000 | EP0733259B1 Improved field memory |
| 02/23/2000 | CN1245580A Method and apparatus for initializing semiconductor memory |
| 02/23/2000 | CN1245338A Semiconductor memory |
| 02/22/2000 | USRE36579 Sense circuit for reading data stored in nonvolatile memory cells |
| 02/22/2000 | US6029210 Memory initialization system selectively outputting a data between a normal data stored in the memory and a fixed value according to a registered access state |
| 02/22/2000 | US6029197 Management information base (MIB) report interface for abbreviated MIB data |
| 02/22/2000 | US6028816 System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor |
| 02/22/2000 | US6028812 Semiconductor memory device and method for controlling the same |
| 02/22/2000 | US6028810 Fast accessible dynamic type semiconductor memory device |
| 02/22/2000 | US6028806 Semiconductor memory with local phase generation from global phase signals and local isolation signals |