Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
10/1999
10/19/1999US5969982 Ferroelectric memory devices having linear reference cells therein and methods of operating same
10/19/1999US5969981 Semiconductor memory device employing ferroelectric memory cell, attaining low power consumption while preventing deterioration of ferroelectric
10/19/1999US5969980 Sense amplifier configuration for a 1T/1C ferroelectric memory
10/19/1999US5969979 Ferroelectric memory device
10/19/1999US5969978 Read/write memory architecture employing closed ring elements
10/19/1999US5969565 Voltage booster circuit
10/19/1999US5969553 Digital delay circuit and digital PLL circuit with first and second delay units
10/19/1999US5969552 Dual loop delay-locked loop
10/19/1999US5969551 Clock generator having DLL and semiconductor device having clock generator
10/19/1999US5969380 Three dimensional ferroelectric memory
10/14/1999DE19830568A1 Ferroelectric memory storage arrangement
10/13/1999EP0949630A2 Clock suspending circuitry
10/13/1999EP0949629A2 Semiconductor integrated circuit having a sleep mode with low power and small area
10/13/1999EP0948819A2 Multiple magnetic tunnel structures
10/13/1999EP0948792A1 Method and apparatus for sharing sense amplifiers between memory banks
10/13/1999EP0843901A4 Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
10/13/1999EP0565079B1 Semiconductor device including voltage stress test shunting circuit
10/13/1999CN1231481A Multivalue semiconductor memory device and error erasing method thereof
10/13/1999CN1231480A Bus central point holding circuit for high-speed memory read operation
10/13/1999CN1231479A SDRAM structure for sequence pulse string mode
10/12/1999US5966731 Protocol for communication with dynamic memory
10/12/1999US5966725 Memory refreshing system having selective execution of self and normal refresh operations for a plurality of memory banks
10/12/1999US5966420 Counter circuit for embodying linear burst sequence
10/12/1999US5966389 Flexible ECC/parity bit architecture
10/12/1999US5966343 Variable latency memory circuit
10/12/1999US5966342 Write control driver circuit and method
10/12/1999US5966341 Semiconductor memory
10/12/1999US5966340 Semiconductor memory device having hierarchical word line structure
10/12/1999US5966338 Integrated circuit
10/12/1999US5966337 Method for overdriving bit line sense amplifier
10/12/1999US5966334 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
10/12/1999US5966332 Floating gate memory cell array allowing cell-by-cell erasure
10/12/1999US5966326 Nonvolatile semiconductor memory equipped with single bit and multi-bit cells
10/12/1999US5966324 Static semiconductor memory device driving bit line potential by bipolar transistor shared by adjacent memory cells
10/12/1999US5966323 Low switching field magnetoresistive tunneling junction for high density arrays
10/12/1999US5966322 Giant magnetoresistive effect memory cell
10/12/1999US5966321 SRAM cell having increased cell ratio
10/12/1999US5966320 SRAM structure having common bit line
10/12/1999US5966319 Static memory device allowing correct data reading
10/12/1999US5966318 Nondestructive readout memory utilizing ferroelectric capacitors isolated from bitlines by buffer amplifiers
10/12/1999US5966317 Memory cell
10/12/1999US5966316 Semiconductor memory device having storage capacity of 22N+1 bits
10/12/1999US5966315 Semiconductor memory having hierarchical bit line architecture with non-uniform local bit lines
10/12/1999US5966045 Semiconductor device having a first stage input unit to which a potential is supplied from external and internal power supplies
10/12/1999US5966012 Magnetic tunnel junction device with improved fixed and free ferromagnetic layers
10/12/1999US5965922 Semiconductor memory device composed of half cells
10/12/1999US5964884 Self-timed pulse control circuit
10/07/1999WO1999050853A1 High resolution multi-bit-per-cell memory
10/07/1999WO1999050852A1 Semiconductor memory asynchronous pipeline
10/07/1999WO1999050833A1 Method and apparatus for magnetic recording
10/07/1999DE19915044A1 Interface for synchronous semiconductor memory e.g. SDRAM
10/07/1999DE19914857A1 Injecting charge carriers into EPROM cell floating gate
10/07/1999DE19910605A1 Protective circuit for semiconductor memory
10/06/1999EP0947994A2 Reduced signal test for dynamic random access memory
10/06/1999EP0947992A2 Sense amplifier circuit
10/06/1999EP0947991A2 Improved dynamic random assess memory circuit and methods therefor
10/06/1999EP0946943A1 Memory and method for sensing sub-groups of memory elements
10/06/1999EP0581309B1 Burn-in test enable circuit of a semiconductor memory device and burn-in test method
10/06/1999CN1230786A Hierarchic flash memory structure and its manufacture
10/06/1999CN1230750A Static semiconductor memory device operating at high speed under lower power supply voltage
10/06/1999CN1045502C Read amplifier circuit and semiconductor memory element
10/05/1999US5963960 Method and apparatus for queuing updates in a computer system
10/05/1999US5963824 Method of making a semiconductor device with adjustable threshold voltage
10/05/1999US5963504 Address transition detection in a synchronous design
10/05/1999US5963503 Synchronous systems having secondary caches
10/05/1999US5963502 Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing
10/05/1999US5963501 Dynamic clock signal generating circuit for use in synchronous dynamic random access memory devices
10/05/1999US5963497 Dynamic random access memory system with simultaneous access and refresh operations and methods for using the same
10/05/1999US5963495 Dynamic sense amplifier with embedded latch
10/05/1999US5963494 Semiconductor memory having bitline precharge circuit
10/05/1999US5963493 Memory device communication line control
10/05/1999US5963491 Semiconductor memory
10/05/1999US5963490 Static semiconductor memory device having a variable power supply voltage applied to a memory cell depending on the state in use and method of testing the same
10/05/1999US5963486 Bit switch circuit and bit line selection method
10/05/1999US5963485 Method and apparatus for bit line recovery in dynamic random access memory
10/05/1999US5963484 High speed single-ended amplifier of a latched type
10/05/1999US5963482 Memory integrated circuit with shared read/write line
10/05/1999US5963481 Integrated circuit
10/05/1999US5963480 Highly compact EPROM and flash EEPROM devices
10/05/1999US5963472 Information storage apparatus and method for operating the same
10/05/1999US5963470 Static semiconductor memory cell with improved data retention stability
10/05/1999US5963469 Vertical bipolar read access for low voltage memory cell
10/05/1999US5963468 Low latency memories and systems using the same
10/05/1999US5963467 Semiconductor memory device
10/05/1999US5963466 Ferroelectric memory having a common plate electrode
10/05/1999US5963465 Symmetric segmented memory array architecture
10/05/1999US5963462 Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method
10/05/1999US5963103 Temperature sensitive oscillator circuit
10/05/1999US5963077 For a semiconductor memory device
10/05/1999US5962902 Semiconductor CMOS device with circuit for preventing latch-up
10/05/1999US5962887 Metal-oxide-semiconductor capacitor
10/05/1999US5962884 Single transistor ferroelectric memory cell with asymmetrical ferroelectric polarization and method of making the same
10/05/1999US5962868 Semiconductor device having contact check circuit
10/05/1999US5961657 Parallel test circuit for semiconductor memory device
10/05/1999CA2135533C All-optical flip-flop
10/01/1999CA2805213A1 Semiconductor memory asynchronous pipeline
09/1999
09/30/1999WO1999031711A3 Precharge circuit for semiconductor memory device
09/30/1999DE19813151A1 Ferromagnetic data store free from problems of relative positioning of a read-write device with a storage device
09/29/1999EP0945981A2 Data latch circuit
09/29/1999EP0945869A1 Method for reading a multiple-level memory cell
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