Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
12/1999
12/15/1999CN1238530A Input receiver circuit
12/15/1999CN1238529A Sense amplifier circuit
12/15/1999CN1238527A Improved dynamic access memory delay circuits and methods therefor
12/15/1999CN1238526A Arrangement for controlling voltage generators in multi-voltage generator chips such as DRAMS
12/15/1999CN1238485A Clock latency compensation circuit for DDR timing
12/14/1999US6003148 Semiconductor memory device allowing repair of a defective memory cell with a redundant circuit in a multibit test mode
12/14/1999US6003121 Single and multiple channel memory detection and sizing
12/14/1999US6002637 Input buffer circuit
12/14/1999US6002636 Semiconductor memory drive capable of canceling power supply noise
12/14/1999US6002635 Semiconductor memory device with control for auxiliary word lines for memory cell selection
12/14/1999US6002634 Sense amplifier latch driver circuit for a 1T/1C ferroelectric memory
12/14/1999US6002631 Semiconductor memory device having a mode in which a plurality of data are simultaneously read out of memory cells of one row and different columns
12/14/1999US6002629 Integrated circuit memory devices having improved refresh mode addressing and methods of operating same
12/14/1999US6002628 Dynamic random access memory device with reduced refresh duration, and corresponding refresh process
12/14/1999US6002625 Cell array and sense amplifier structure exhibiting improved noise characteristic and reduced size
12/14/1999US6002624 Semiconductor memory device with input/output masking function without destruction of data bit
12/14/1999US6002620 Method and apparatus of column redundancy for non-volatile analog and multilevel memory
12/14/1999US6002616 Reference voltage generating circuit of sense amplifier using residual data line
12/14/1999US6002615 Clock shift circuit and synchronous semiconductor memory device using the same
12/14/1999US6002614 Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
12/14/1999US6002613 Data communication for memory
12/14/1999US6002611 Fast, low current program with auto-program for flash memory
12/14/1999US6002608 Ferroelectric memory and writing method of therein
12/14/1999US6002607 Read-only-memory (ROM) having a memory cell that stores a plurality of bits of information
12/14/1999US6002606 Semiconductor memory device
12/14/1999US6002286 Apparatus and method for a programmable interval timing generator in a semiconductor memory
12/14/1999US6002275 Single ended read write drive for memory
12/14/1999US6002162 Overall VPP well form
12/14/1999US6002152 EEPROM with split gate source side injection with sidewall spacers
12/14/1999US6001680 Static random memory device
12/09/1999WO1999063598A1 Semiconductor current-switching device having operational enhancer and method therefor
12/09/1999WO1999063542A1 Radiation hardened six transistor random access memory and memory device
12/08/1999EP0963083A2 Method of and apparatus for correctly transmitting signals at high speed without waveform distortion
12/08/1999EP0962940A1 Method and apparatus capable of trimming a nonvolatile semiconductor storage device without any superfluous pads or terminals
12/08/1999EP0962939A1 Magnetic memory cell
12/08/1999CN1237769A Semiconductor memory device and method of burn-in testing
12/08/1999CN1237768A Dram incorporating self refresh control circuit and system LSI including the dram
12/08/1999CN1237767A Semiconductor memory device
12/08/1999CN1237766A Multiple bit magnetic memory cell
12/08/1999CN1047262C Semiconductor device capable of reducing power dissipation in stand-by state
12/08/1999CN1047249C Semiconductor memory device
12/07/1999US5999483 Semiconductor circuit device operating in synchronization with clock signal
12/07/1999US5999481 Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals
12/07/1999US5999480 Dynamic random-access memory having a hierarchical data path
12/07/1999US5999478 Highly integrated tri-port memory buffers having fast fall-through capability and methods of operating same
12/07/1999US5999474 Method and apparatus for complete hiding of the refresh of a semiconductor memory
12/07/1999US5999473 Circuit and method for internal refresh counter
12/07/1999US5999472 Multi-bank synchronous semiconductor memory device with easy control
12/07/1999US5999471 Semiconductor memory device having a refresh function and a method for refreshing the same
12/07/1999US5999470 Sense amplifier circuit having high speed operation
12/07/1999US5999467 Method and apparatus for stress testing a semiconductor memory
12/07/1999US5999464 Semiconductor memory device and method of checking same for defect
12/07/1999US5999463 Redundancy fuse box and semiconductor device including column redundancy fuse box shared by a plurality of memory blocks
12/07/1999US5999461 Low voltage bootstrapping circuit
12/07/1999US5999460 Semiconductor memory device
12/07/1999US5999458 Latch circuit, data output circuit and semiconductor device having the circuits
12/07/1999US5999453 Nonvolatile semiconductor memory
12/07/1999US5999446 Multi-state flash EEprom system with selective multi-sector erase
12/07/1999US5999445 Multilevel non-volatile memory devices
12/07/1999US5999442 Semi-conductor device with a memory cell
12/07/1999US5999441 Random access memory having bit selectable mask for memory writes
12/07/1999US5999440 Embedded DRAM with noise-protecting substrate isolation well
12/07/1999US5999439 Ferroelectric memory using ferroelectric reference cells
12/07/1999US5999438 Ferroelectric storage device
12/07/1999US5999436 Semiconductor storage apparatus having an activation signal generating circuitry disposed both on the inside and in between the sense amplifier areas
12/07/1999US5999197 Synchronized data processing system and image processing system
12/07/1999US5999039 Active power supply filter
12/07/1999US5999031 Semiconductor device with bus line loading compensation circuit
12/07/1999US5999027 Phase compensating apparatus and delay controlling circuit
12/07/1999US5999021 Pad signal detecting circuit in a semiconductor device for detecting a reference voltage in a high-speed interface
12/07/1999US5999009 Semiconductor integrated circuit with an internal voltage generating circuit requiring a reduced occupied area
12/02/1999WO1999062069A1 Magnetoresistive random access memory and method for reading/writing digital information to such a memory
12/02/1999WO1999062068A2 Magnetic memory
12/02/1999DE19923979A1 Ferroelectric memory with split wordline structure
12/02/1999DE19908513A1 Semiconductor memory device with parallel bit test mode
12/02/1999DE19904054A1 DRAM mit Selbstauffrischungssteuerschaltung und LSI-System mit dem DRAM DRAM self-refresh control circuit and system LSI with DRAM
12/02/1999DE19825391A1 Magnetischer Speicher Magnetic memory
12/02/1999DE19823956A1 Anordnung zur Übersprechdämpfung in Wortleitungen von DRAM-Schaltungen Arrangement for crosstalk in word lines of DRAM circuits
12/02/1999DE19823826A1 MRAM-Speicher sowie Verfahren zum Lesen/Schreiben digitaler Information in einen derartigen Speicher MRAM memory, as well as methods for reading / writing digital information in such a memory
12/01/1999EP0961287A1 High storage capacity non-volatile memory
12/01/1999EP0961286A2 DRAM word line crosstalk reduction
12/01/1999EP0961284A2 Semiconductor memory device and data processing methods thereof
12/01/1999EP0961282A2 Semiconductor memory device exhibiting improved high speed and stable write operations
12/01/1999EP0961281A1 Semiconductor memory circuit
12/01/1999EP0960536A2 Queuing structure and method for prioritization of frames in a network switch
12/01/1999EP0960512A1 Apparatus and method for synthesizing management packets for transmission between a network switch and a host controller
12/01/1999EP0960422A1 Method for minimizing the access time for semiconductor memories
12/01/1999EP0960421A1 Bitline load and precharge structure for an sram memory
12/01/1999EP0731969B1 Magnetic multilayer device including a resonant-tunneling double-barrier structure
12/01/1999EP0704854B1 Memory device having error detection and correction function, and methods for writing and erasing the memory device
12/01/1999CN1236995A Element exploiting magnetic material and addressing method therefor
12/01/1999CN1236987A Method for fabricating ferroelectric integrated circuits
12/01/1999CN1236956A Level detecting circuit
12/01/1999CN1236954A Structure for echo IC
12/01/1999CN1236953A Data latch circuit
11/1999
11/30/1999US5996108 Memory system
11/30/1999US5996096 Dynamic redundancy for random access memory assemblies
11/30/1999US5996052 Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array
11/30/1999US5996043 Two step memory device command buffer apparatus and method and memory devices and computer systems using same
11/30/1999US5995443 Synchronous memory device
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