| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 05/23/2002 | US20020060949 Method and circuit for driving quad data rate synchronous semiconductor memory device |
| 05/23/2002 | US20020060946 Synchronous semiconductor memory device and method for operating same |
| 05/23/2002 | US20020060945 Synchronous semiconductor device and method for latching input signals |
| 05/23/2002 | US20020060944 Semiconductor integrated circuit device and method of activating the same |
| 05/23/2002 | US20020060943 Semiconductor device having early operation high voltage generator and high voltage supplying method therefore |
| 05/23/2002 | US20020060942 Semiconductor memory device with internal power supply potential genaration circuit |
| 05/23/2002 | US20020060941 Antifuse detection circuit |
| 05/23/2002 | US20020060940 Semiconductor memory |
| 05/23/2002 | US20020060933 Semiconductor device and multichip module |
| 05/23/2002 | US20020060931 Semiconductor memory circuit |
| 05/23/2002 | US20020060930 Semiconductor integrated circuit device |
| 05/23/2002 | US20020060928 Memory cell of nonvolatile semiconductor memory device |
| 05/23/2002 | US20020060927 Non-volatile read only memory and its manufacturing method |
| 05/23/2002 | US20020060925 Dram memory cell |
| 05/23/2002 | US20020060924 Semiconductor memory |
| 05/23/2002 | US20020060923 Addressing of memory matrix |
| 05/23/2002 | US20020060922 Method for detecting polarization of a ferroelectric capacitor in a ferroelectric memory and thereof structure |
| 05/23/2002 | US20020060920 Semiconductor memory with built-in cache |
| 05/23/2002 | US20020060337 Nonvolatile memory, cell array thereof , and method for sensing data therefrom |
| 05/23/2002 | DE10056282A1 Artificial neuron comprises a transistor and a number of electrical contacts which can be contacted by the ends of nanostructures |
| 05/23/2002 | DE10056159A1 Magneto-resistive random-access memory device uses selection transistors of wide channel width associated with several magnetic tunnel junction memory cells |
| 05/23/2002 | DE10055936A1 Magnetoresistive memory has optimized line shape so that magnetic field components in plane of cell field decrease rapidly with increasing distance from matrix intersection |
| 05/23/2002 | DE10053966A1 DRAM-Speicherzelle DRAM memory cell |
| 05/23/2002 | DE10045042C1 MRAM-Modulanordnung MRAM module arrangement |
| 05/23/2002 | CA2429028A1 Magnetic logic elements |
| 05/22/2002 | EP1207564A2 Magnetoresistive device and/or multiple element magnetoresistive device |
| 05/22/2002 | EP1207538A1 Magnetic Random Access Memory with improved breakdown voltage |
| 05/22/2002 | EP1206776A1 Pseudo-differential current sense amplifier with hysteresis |
| 05/22/2002 | CN1350301A High-speed synchronous semiconductor memory having multi-level line-pipe structure and method of operating said memory |
| 05/21/2002 | US6393577 Semiconductor integrated circuit system, semiconductor integrated circuit and method for driving semiconductor integrated circuit system |
| 05/21/2002 | US6393575 Semiconductor device having input buffers |
| 05/21/2002 | US6393548 Variable 16 or 32 bit PCI interface which supports steering and swapping of data |
| 05/21/2002 | US6393542 Electronic circuit system and interface circuit that compares read and write clock operations |
| 05/21/2002 | US6393541 Data transfer memory having the function of transferring data on a system bus |
| 05/21/2002 | US6393504 Dynamic address mapping and redundancy in a modular memory device |
| 05/21/2002 | US6393378 Circuit and method for specifying performance parameters in integrated circuits |
| 05/21/2002 | US6393080 Apparatus comprising clock control circuit and device using internal clock signal synchronized to external clock signal |
| 05/21/2002 | US6393021 Integrated multiport switch having shared data receive FIFO structure |
| 05/21/2002 | US6392958 Asynchronous SRAM compatible memory device using DRAM cell and method for driving the same |
| 05/21/2002 | US6392956 Semiconductor memory that enables high speed operation |
| 05/21/2002 | US6392955 Circuit for eliminating idle cycles in a memory device |
| 05/21/2002 | US6392954 Dual port programmable logic device variable depth and width memory array |
| 05/21/2002 | US6392953 Semiconductor memory |
| 05/21/2002 | US6392952 Memory refresh circuit and memory refresh method |
| 05/21/2002 | US6392951 Semiconductor storage device |
| 05/21/2002 | US6392950 Semiconductor device including multi-chip |
| 05/21/2002 | US6392949 High performance memory architecture |
| 05/21/2002 | US6392948 Semiconductor device with self refresh test mode |
| 05/21/2002 | US6392947 Semiconductor memory device |
| 05/21/2002 | US6392946 SDR and QDR converter and interface card, motherboard and memory module interface using the same |
| 05/21/2002 | US6392945 Semiconductor memory device |
| 05/21/2002 | US6392944 Semiconductor memory device capable of performing stable sensing operation even under low power supply voltage environment |
| 05/21/2002 | US6392942 Semiconductor memory device having a multi-layer interconnection structure suitable for merging with logic |
| 05/21/2002 | US6392940 Semiconductor memory circuit |
| 05/21/2002 | US6392939 Semiconductor memory device with improved defect elimination rate |
| 05/21/2002 | US6392937 Redundancy circuit of semiconductor memory |
| 05/21/2002 | US6392932 Nonvolatile memory system, semiconductor memory, and writing method |
| 05/21/2002 | US6392931 Method for high precision programming nonvolatile memory cells, with optimized programming speed |
| 05/21/2002 | US6392924 Array for forming magnetoresistive random access memory with pseudo spin valve |
| 05/21/2002 | US6392923 Magnetoresistive midpoint generator and method |
| 05/21/2002 | US6392922 Passivated magneto-resistive bit structure and passivation method therefor |
| 05/21/2002 | US6392921 Driving circuit for non destructive non volatile ferroelectric random access memory |
| 05/21/2002 | US6392920 Nonvolatile memory and its driving method |
| 05/21/2002 | US6392919 Reduction of imprint in ferroelectric devices using a depoling technique |
| 05/21/2002 | US6392918 Circuit configuration for generating a reference voltage for reading a ferroelectric memory |
| 05/21/2002 | US6392917 Nonvolatile ferroelectric memory and method for fabricating the same |
| 05/21/2002 | US6392916 Circuit for providing an adjustable reference voltage for long-life ferroelectric random access memory device |
| 05/21/2002 | US6392911 Reduced power bit line selection in memory circuits |
| 05/21/2002 | US6392909 Semiconductor memory device having fixed CAS latency in normal operation and various CAS latencies in test mode |
| 05/21/2002 | US6392456 Analog mixed digital DLL |
| 05/21/2002 | US6392445 Decoder element for producing an output signal having three different potentials |
| 05/21/2002 | US6392394 Step-down circuit for reducing an external supply voltage |
| 05/21/2002 | US6392303 Digit line architecture for dynamic memory |
| 05/21/2002 | US6392284 Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer |
| 05/21/2002 | US6392281 Ferromagnetic tunnel junction device and method of forming the same |
| 05/21/2002 | US6391483 Circular magnetic configuration; word line for producing radial magnetic field; computers |
| 05/16/2002 | WO2002039456A1 Semiconductor memory and method of control thereof |
| 05/16/2002 | WO2002039455A2 Mram arrangement with selection transistors of large channel width |
| 05/16/2002 | WO2002039454A2 Magnetoresistive memory (mram) |
| 05/16/2002 | WO2002039453A1 Distributed storage in semiconductor memory systems |
| 05/16/2002 | WO2002025665A3 Non-volatile passive matrix and method for readout of the same |
| 05/16/2002 | WO2001043135A9 A prefetch write driver for a random access memory |
| 05/16/2002 | US20020059496 Memory interface circuit |
| 05/16/2002 | US20020059488 Data transfer control device and electronic instrument |
| 05/16/2002 | US20020059323 Synchronous dynamic random access memory |
| 05/16/2002 | US20020058158 Magneto-resistance effect element magneto-resistance effect memory cell, MRAM, and method for performing information write to or read from the magneto-resistance effect memory cell |
| 05/16/2002 | US20020058148 Magnetic device and solid-state magnetic memory |
| 05/16/2002 | US20020057622 Data sensing circuit of semiconductor memory |
| 05/16/2002 | US20020057620 Semiconductor integrated circuit device and method of activating the same |
| 05/16/2002 | US20020057619 Semiconductor integrated circuit device and method of activating the same |
| 05/16/2002 | US20020057618 Semiconductor integrated circuit device having hierarchical power source arrangement |
| 05/16/2002 | US20020057617 Transparent continuous refresh ram cell architecture |
| 05/16/2002 | US20020057616 Semiconductor memory device |
| 05/16/2002 | US20020057615 Semiconductor memory device |
| 05/16/2002 | US20020057614 Semiconductor integrated circuit |
| 05/16/2002 | US20020057613 Random access memory device |
| 05/16/2002 | US20020057612 Signal transmission circuit and semiconductor memory using the same |
| 05/16/2002 | US20020057611 Semiconductor memory device |
| 05/16/2002 | US20020057607 Activation of word lines in semiconductor memory device |
| 05/16/2002 | US20020057606 Method and apparatus for modeling a neural synapse function by utilizing a single conventional MOSFET |