| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
|---|
| 04/11/2002 | US20020041536 Semiconductor memory and method of operating the same |
| 04/11/2002 | US20020041535 Full page increment/decrement burst for DDR SDRAM/SGRAM |
| 04/11/2002 | US20020041533 Fuse circuit using anti-fuse and method for searching for failed address in semiconductor memory |
| 04/11/2002 | US20020041532 Semiconductor memory device having high data input/output frequency and capable of efficiently testing circuit associated with data input/output |
| 04/11/2002 | US20020041531 Semiconductor integrated circuit device |
| 04/11/2002 | US20020041528 Semiconductor integrated circuit device and control method therefor |
| 04/11/2002 | US20020041524 Semiconductor integrated circuit |
| 04/11/2002 | US20020041523 High speed data bus |
| 04/11/2002 | US20020041522 High speed data bus |
| 04/11/2002 | US20020041519 Single electron resistor memory device and method |
| 04/11/2002 | US20020041516 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
| 04/11/2002 | US20020041515 Magnetization reversal methods for magnetic film, magnetoresistive films, and magnetic memories using them |
| 04/11/2002 | US20020041514 Memory cell configuration and method for its production |
| 04/11/2002 | US20020041513 Variable capacitor and memory device employing the same |
| 04/11/2002 | US20020041512 Semiconductor memory and method for driving the same |
| 04/11/2002 | US20020041511 Two-dimensional resonant tunneling diode memory cell |
| 04/11/2002 | US20020041510 Semiconductor storage device |
| 04/11/2002 | US20020041198 Area efficient redundancy multiplexer circuit technique for integrated circuit devices providing significantly reduced parasitic capacitance |
| 04/11/2002 | US20020041194 Semiconductor integrated circuit having output buffer |
| 04/11/2002 | US20020041015 Semiconductor chip, semiconductor device, methods of fabricating thereof, circuit board and electronic device |
| 04/11/2002 | US20020041004 Monolithically integrable inductor |
| 04/11/2002 | US20020040992 Nonvolatile semiconductor memory |
| 04/11/2002 | US20020040989 Semiconductor storage device and method of testing the same |
| 04/11/2002 | DE10129928A1 Halbleiterspeichervorrichtung mit einem für hohe Integration geeigneten Aufbau A semiconductor memory device having a structure suitable for high integration |
| 04/10/2002 | EP1195820A2 Integrated magnetoresistive circuit |
| 04/10/2002 | EP1195771A2 Differential voltage sense circuit to detect the state of a CMOS process compatible fuses at low supply voltages |
| 04/10/2002 | EP0954866B1 Sdram clocking test mode |
| 04/10/2002 | EP0668561B1 A flexible ECC/parity bit architecture |
| 04/10/2002 | CN1344415A Integrated memory with memory cells and reference cells and operating method for memory of this type |
| 04/10/2002 | CN1343987A Semiconductor memory device and memory modulus and system adopting same |
| 04/10/2002 | CN1343986A Magnetic resistance memory modulus |
| 04/10/2002 | CN1343985A Magnetic resistance memory and its reading method |
| 04/10/2002 | CN1343969A Mfg. method of cork electromagnhetic resistance head |
| 04/10/2002 | CN1082765C 数据存储装置 Data storage means |
| 04/09/2002 | USRE37641 Dynamic random access memory using imperfect isolating transistors |
| 04/09/2002 | US6370612 Adaptive memory control |
| 04/09/2002 | US6370080 Semiconductor memory for logic-hybrid memory |
| 04/09/2002 | US6370079 Integrated circuits having reduced timing skew among signals transmitted therein using opposingly arranged selection circuits |
| 04/09/2002 | US6370077 Dynamic random access memory device and semiconductor integrated circuit device |
| 04/09/2002 | US6370075 Charge pump circuit adjustable in response to an external voltage source |
| 04/09/2002 | US6370073 Single-port multi-bank memory system having read and write buffers and method of operating same |
| 04/09/2002 | US6370072 Low voltage single-input DRAM current-sensing amplifier |
| 04/09/2002 | US6370069 Method for testing a multiplicity of word lines of a semiconductor memory configuration |
| 04/09/2002 | US6370067 Automatic configuration of delay parameters in a dynamic memory controller |
| 04/09/2002 | US6370062 NAND-type flash memory device and method of operating the same |
| 04/09/2002 | US6370058 Non-volatile semiconductor memory device and system LSI including the same |
| 04/09/2002 | US6370057 Semiconductor memory device having plate lines and precharge circuits |
| 04/09/2002 | US6370056 Ferroelectric memory and method of operating same |
| 04/09/2002 | US6370054 Dynamic RAM and semiconductor device |
| 04/09/2002 | US6369630 Single-event upset hardened reconfigurable bi-stable CMOS latch |
| 04/09/2002 | US6369627 Delay circuit and semiconductor integrated circuit having same |
| 04/09/2002 | US6369617 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit |
| 04/09/2002 | US6369615 Semiconductor integrated circuit and pulse signal generating method |
| 04/09/2002 | US6368878 Intentional asymmetry imposed during fabrication and/or access of magnetic tunnel junction devices |
| 04/04/2002 | WO2002027729A2 Writable tracking cells |
| 04/04/2002 | WO2002005470A3 Magnetoresistive trimming of gmr circuits |
| 04/04/2002 | US20020040437 Semiconductor memory device internally provided with logic circuit which can be readily controlled and controlling method thereof |
| 04/04/2002 | US20020040424 Memory controller that controls supply timing of read data |
| 04/04/2002 | US20020040420 Simply interfaced semiconductor integrated circuit device including logic circuitry and embedded memory circuitry |
| 04/04/2002 | US20020040417 Programmable refresh scheduler for embedded DRAMs |
| 04/04/2002 | US20020040416 Memory controller with power management logic |
| 04/04/2002 | US20020039834 Gate device with raised channel and method |
| 04/04/2002 | US20020039668 First and second magnetic layers have respective first and second magnetizations in an anti-parallel relationship in a state no substantial writing magnetic field is applied. |
| 04/04/2002 | US20020039361 Memory used in packet switching network for successively storing data bits in data storage region and serially outputting data bits and method used therein |
| 04/04/2002 | US20020039326 Clock synchronous circuit |
| 04/04/2002 | US20020039324 Semiconductor memory device having altered clock freqency for address and/or command signals, and memory module and system having the same |
| 04/04/2002 | US20020039323 Semiconductor device |
| 04/04/2002 | US20020039322 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
| 04/04/2002 | US20020039321 Serial access memory |
| 04/04/2002 | US20020039320 Semiconductor memory device and bit line isolation gate arrangement method thereof |
| 04/04/2002 | US20020039317 High performance erasable programmable read-only memory (EPROM) devices with multiple dimension first-level bit lines |
| 04/04/2002 | US20020039316 Semiconductor memory device operating at high speed with low current consumption |
| 04/04/2002 | US20020039315 Synchronous semiconductor memory device having improved operational frequency margin at data input/output |
| 04/04/2002 | US20020039309 Magneto-resistive memory having sense amplifier with offset control |
| 04/04/2002 | US20020039308 MRAM configuration |
| 04/04/2002 | US20020039307 Data memory device |
| 04/04/2002 | US20020039045 Apparatus for providing both supports including synchronous dynamic random access memory (SDRAM) module and double data rate (DDR) DRAM module |
| 04/04/2002 | US20020038878 Semiconductor memory device having redundancy function |
| 04/04/2002 | US20020038876 Method to produce data cell region and system region for semiconductor memory |
| 04/04/2002 | DE10101735C1 Switch stage acting as input buffer for dynamic random-access memory has difference stage coupled via level converter to memory element providing output signal |
| 04/04/2002 | DE10045692A1 Integrierter Speicher mit Speicherzellen und Pufferkapazitäten Integrated memory having memory cells and buffer capacity |
| 04/04/2002 | DE10043947A1 Current conductor of integrated circuit, producing magnetic field with transitive effect, includes recess modifying field produced |
| 04/03/2002 | EP1193872A1 Reset circuit comprising a ferroelectric capacitor |
| 04/03/2002 | EP1193778A2 Magnetization reversal methods for magnetic film, magnetoresistive films, and magnetic memories using them |
| 04/03/2002 | EP1193715A1 Nonvolatile memory device, having parts with different access time, reliability and capacity |
| 04/03/2002 | EP1193714A2 High-speed bank select multiplexer latch |
| 04/03/2002 | EP1193598A1 Integrated memory with magnetoresistive memory cells |
| 04/03/2002 | EP1192666A1 Memory cell arrangement |
| 04/03/2002 | EP1192648A2 Metal oxide thin films for high dielectric constant applications |
| 04/03/2002 | EP0734573B1 Application specific modules in a programmable logic device |
| 04/03/2002 | CN1343359A Read/write architecture for MRAM |
| 04/03/2002 | CN1343010A 2T-1C ferroelectric random access memory and its operation method |
| 04/03/2002 | CN1343008A Drive method for semiconductor memory |
| 04/03/2002 | CN1342983A 半导体集成电路器件 The semiconductor integrated circuit device |
| 04/03/2002 | CN1082250C Semiconductor memory device having hierarchical bit line structure |
| 04/02/2002 | US6367065 Method and apparatus for N-Nary logic circuit design tool with precharge circuit evaluation |
| 04/02/2002 | US6366693 Digital image region detection method and apparatus |
| 04/02/2002 | US6366611 Circuit for controlling equalization pulse width |
| 04/02/2002 | US6366527 Circuit configuration for generating an output clock signal with optimized signal generation time |
| 04/02/2002 | US6366526 Static random access memory (SRAM) array central global decoder system and method |