| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 06/04/2002 | US6400631 Circuit, system and method for executing a refresh in an active memory bank |
| 06/04/2002 | US6400629 System and method for early write to memory by holding bitline at fixed potential |
| 06/04/2002 | US6400627 Sensing circuit for magnetic memory unit |
| 06/04/2002 | US6400626 Memory devices |
| 06/04/2002 | US6400625 Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester |
| 06/04/2002 | US6400624 Configure registers and loads to tailor a multi-level cell flash design |
| 06/04/2002 | US6400623 Semiconductor memory having parallel test mode |
| 06/04/2002 | US6400621 Semiconductor memory device and method of checking same for defect |
| 06/04/2002 | US6400619 Micro-cell redundancy scheme for high performance eDRAM |
| 06/04/2002 | US6400617 Semiconductor memory circuit having selective redundant memory cells |
| 06/04/2002 | US6400616 Method of an apparatus for correctly transmitting signals at high speed without waveform distortion |
| 06/04/2002 | US6400612 Memory based on a four-transistor storage cell |
| 06/04/2002 | US6400607 Reading circuit for a non-volatile memory |
| 06/04/2002 | US6400601 Nonvolatile semiconductor memory device |
| 06/04/2002 | US6400600 Method of repairing defective tunnel junctions |
| 06/04/2002 | US6400596 Semiconductor memory device using open data line arrangement |
| 06/04/2002 | US6400595 256 meg dynamic access memory |
| 06/04/2002 | US6400213 Level detection by voltage addition/subtraction |
| 05/30/2002 | WO2002043073A1 Method and system for dual bit memory erase verification |
| 05/30/2002 | WO2002043072A2 Very small swing and low voltage cmos static memory |
| 05/30/2002 | WO2002043071A1 A ferroelectric memory circuit and method for its fabrication |
| 05/30/2002 | WO2002043070A1 A method for non-destructive readout and apparatus for use with the method |
| 05/30/2002 | WO2002043067A2 Integrated memory with an arrangement of non-volatile memory cells and method for the production and operation of an integrated memory |
| 05/30/2002 | WO2002005281A3 A high speed dram architecture with uniform access latency |
| 05/30/2002 | WO2002003459A3 High-speed low-power semiconductor memory architecture |
| 05/30/2002 | WO2001097373A3 Multiple output current mirror with improved accuracy |
| 05/30/2002 | WO2001093271A3 MULTI-GENERATOR, PARTIAL ARRAY Vt, TRACKING SYSTEM TO IMPROVE ARRAY RETENTION TIME |
| 05/30/2002 | US20020066058 Synchronous semiconductor device, and inspection system and method for the same |
| 05/30/2002 | US20020066052 Method and apparatus for scheduling and using memory calibrations to reduce memory errors in high speed memory devices |
| 05/30/2002 | US20020066001 Adaptive calibration technique for high speed memory devices |
| 05/30/2002 | US20020065997 Multi-port memory device and system for addressing the multi-port memory device |
| 05/30/2002 | US20020065978 Method and apparatus for protecting flash memory |
| 05/30/2002 | US20020064898 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device |
| 05/30/2002 | US20020064083 Clock generating circuits controlling activation of a delay locked loop circuit on transition to a standby mode of a semiconductor memory device and methods for operating the same |
| 05/30/2002 | US20020064079 Semiconductor memory device having a plurality of low power consumption modes |
| 05/30/2002 | US20020064075 Semiconductor memory device with reduced interference between bit lines |
| 05/30/2002 | US20020064073 Dram module and method of using sram to replace damaged dram cell |
| 05/30/2002 | US20020064072 Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode |
| 05/30/2002 | US20020064070 Non-volatile memory and semiconductor device |
| 05/30/2002 | US20020064069 Memory cell configuration and method for fabricating it |
| 05/30/2002 | US20020064068 Method and apparatus for non-volatile memory storage |
| 05/30/2002 | US20020064067 Semiconductor memory device |
| 05/30/2002 | US20020064065 Methods of forming and reading ferroelectric memory cells |
| 05/30/2002 | US20020064004 Magnetoresistive double spin filter tunnel junction |
| 05/30/2002 | US20020063595 Circuit configuration with internal supply voltage |
| 05/30/2002 | US20020063576 Programmable impedance control circuit |
| 05/29/2002 | EP1209687A2 A synthesizable synchronous static RAM |
| 05/29/2002 | EP1208567A1 Double data rate scheme for data output |
| 05/29/2002 | EP1002369B1 Synchronous clock generator including delay-locked loop |
| 05/29/2002 | EP0792506B1 Refresh strategy for drams |
| 05/29/2002 | DE10155102A1 Verfahren und Vorrichtung zum Auffrischen (Refreshing) von Halbleiterspeichern Method and apparatus for refreshing (Refreshing) of semiconductor memories |
| 05/29/2002 | DE10145646A1 Producing position error signal in recording system for holographically represented data. involves forming image of each holographically recorded pixel on at least 2 adjacent camera pixels |
| 05/29/2002 | DE10136503A1 Sense amplifier integrated circuit for high speed semiconductor memory, has current amplifier with input stage and output stage which are responsive to control signal that reduces gain of current amplifier |
| 05/29/2002 | DE10121708A1 Halbleiterspeichereinrichtung und Verfahren zum Ändern von Ausgangsdaten dieser Einrichtung Semiconductor memory device and method of changing output data of this institution |
| 05/29/2002 | DE10057489A1 Integrated memory has memory cell field and control circuit connected to deactivation switch with delay stage activated by selection signal for delaying switching process |
| 05/29/2002 | DE10056830A1 Integrierte magnetoresistive Halbleiterspeicheranordnung Integrated magnetoresistive semiconductor memory device |
| 05/29/2002 | CN1351382A Self alignment of semiconductor memory array having floating gate memory units with control gate isolating sheets |
| 05/29/2002 | CN1351381A Semiconductor memory unit and array using ultra-thin medium breakdown phenomenon |
| 05/29/2002 | CN1351379A Memory recording device, reading-out device, recording and reading-out devices |
| 05/29/2002 | CN1351349A 半导体存储器 Semiconductor memory |
| 05/28/2002 | US6397365 Memory error correction using redundant sliced memory and standard ECC mechanisms |
| 05/28/2002 | US6397364 Digital data representation for multi-bit data storage and transmission |
| 05/28/2002 | US6397312 Memory subsystem operated in synchronism with a clock |
| 05/28/2002 | US6396768 Synchronous semiconductor memory device allowing easy and fast test |
| 05/28/2002 | US6396766 Semiconductor memory architecture for minimizing input/output data paths |
| 05/28/2002 | US6396763 DRAM having a reduced chip size |
| 05/28/2002 | US6396761 Semiconductor integrated circuit device and method of activating the same |
| 05/28/2002 | US6396758 Semiconductor memory device |
| 05/28/2002 | US6396757 Multiple output current mirror with improved accuracy |
| 05/28/2002 | US6396756 Integrated circuit memory devices including transmission parts that are adjacent input/output selection parts |
| 05/28/2002 | US6396754 Semiconductor memory device which controls sense amplifier for detecting bit line bridge and method of controlling the semiconductor memory device |
| 05/28/2002 | US6396748 Method and apparatus for setting redundancy data for semiconductor memory device |
| 05/28/2002 | US6396747 Semiconductor memory device capable of high speed input/output of wide bandwidth data by improving usage efficiency of external data bus |
| 05/28/2002 | US6396746 Semiconductor memory device |
| 05/28/2002 | US6396744 Flash memory with dynamic refresh |
| 05/28/2002 | US6396742 Testing of multilevel semiconductor memory |
| 05/28/2002 | US6396741 Programming of nonvolatile memory cells |
| 05/28/2002 | US6396737 High density flash memory architecture with columnar substrate coding |
| 05/28/2002 | US6396736 Nonvolatile semiconductor memory device which stores multi-value information |
| 05/28/2002 | US6396735 Magnetic memory element, magnetic memory and manufacturing method of magnetic memory |
| 05/28/2002 | US6396733 Magneto-resistive memory having sense amplifier with offset control |
| 05/28/2002 | US6396732 Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system |
| 05/28/2002 | US6396731 SRAM cell employing tunnel switched diode |
| 05/28/2002 | US6396730 Non-volatile memory cell and sensing method |
| 05/28/2002 | US6396336 Sleep mode VDD detune for power reduction |
| 05/28/2002 | US6396323 Phase adjustor for semiconductor integrated circuit |
| 05/28/2002 | US6396322 Delay locked loop of a DDR SDRAM |
| 05/28/2002 | US6396320 Clock control method and circuit |
| 05/28/2002 | US6396310 Current sense amplifiers enabling amplification of bit line voltages provided by bit line sense amplifiers |
| 05/28/2002 | US6396111 Semiconductor integrated circuit device having capacitor element |
| 05/28/2002 | US6396095 Semiconductor memory and method of driving semiconductor memory |
| 05/28/2002 | US6396088 System with meshed power and signal buses on cell array |
| 05/23/2002 | WO2002041492A1 Magnetic logic elements |
| 05/23/2002 | WO2002041321A1 Integrated magnetoresistive semiconductor memory system |
| 05/23/2002 | WO2001085884A3 Predictive timing calibration for memory devices |
| 05/23/2002 | WO2001084561A3 Tunable devices incorporating bicu3ti3feo¿12? |
| 05/23/2002 | US20020062473 Semiconductor device and semiconductor storage device testing method |
| 05/23/2002 | US20020062430 Memory configuration with a central connection area |
| 05/23/2002 | US20020062428 Synchronous dram utilizable as shared memory |
| 05/23/2002 | US20020061606 Semiconductor wafer, semiconductor chip, semiconductor device and method for manufacturing semiconductor device |