G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor

Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
11/2004
11/25/2004	US20040236872 Input/output byte control device using nonvolatile ferroelectric register
11/25/2004	US20040235247 Asymmetric crystalline structure memory cell
11/25/2004	US20040235204 Programmable structure, an array including the structure, and methods of forming the same
11/25/2004	US20040235202 Magnetoresistive element and method for producing the same, as well as magnetic head, magnetic memory and magnetic recording device using the same
11/25/2004	US20040235200 Oxygen content system and method for controlling memory resistance properties
11/25/2004	US20040233774 Semiconductor memory device
11/25/2004	US20040233773 Circuit and method for generating output control signal in synchronous semiconductor memory device
11/25/2004	US20040233770 Dynamic ram-and semiconductor device
11/25/2004	US20040233765 Structure and method for transferring column address
11/25/2004	US20040233764 Semiconductor memory device having self-precharge function
11/25/2004	US20040233763 Semiconductor memory device using magneto resistive element and method of manufacturing the same
11/25/2004	US20040233762 Flash memory
11/25/2004	US20040233761 Magnetic storage device
11/25/2004	US20040233760 Magnetic random access memory array with coupled soft adjacent magnetic layer
11/25/2004	US20040233759 Data memory circuit
11/25/2004	US20040233758 SRAM-compatible memory device having three sense amplifiers between two memory blocks
11/25/2004	US20040233756 Synchronous semiconductor memory device
11/25/2004	US20040233755 Magnetic memory device and its recording control method
11/25/2004	US20040233753 Semiconductor memory
11/25/2004	US20040233751 Methods for erasing flash memory
11/25/2004	US20040233747 RAM store and control method therefor
11/25/2004	US20040233745 Dynamic memory and method for testing a dynamic memory
11/25/2004	US20040233744 Ferroelectric memory with wide operating voltage and multi-bit storage per cell
11/25/2004	US20040233743 Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices
11/25/2004	US20040233741 Half density ROM embedded DRAM
11/25/2004	US20040233737 Circuit arrangement and method for setting a voltage supply for a read/write amplifier of an integrated memory
11/25/2004	US20040233735 Current mode output driver
11/25/2004	US20040233727 Programming verification method of nonvolatile memory cell, semiconductor memory device, and portable electronic apparatus having the semiconductor memory device
11/25/2004	US20040233726 Programming verification method of nonvolatile memory cell, semiconductor memory device, and portable electronic apparatus having the semiconductor memory device
11/25/2004	US20040233725 Programming method of nonvolatile memory cell, semiconductor memory device, and portable electronic appartaus having the semiconductor memory device
11/25/2004	US20040233723 Voltage regulation system for a multiword programming of a low integration area non volatile memory
11/25/2004	US20040233720 Non-volatile semiconductor memory device
11/25/2004	US20040233716 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
11/25/2004	US20040233715 Channel erase type nonvolatile semiconductor memory device and electronic card and electronic apparatus using the device
11/25/2004	US20040233714 Semiconductor memory device and portable electronic apparatus
11/25/2004	US20040233712 Magnetic storage cell
11/25/2004	US20040233711 Magnetic memory device
11/25/2004	US20040233710 Method and system for data communication on a chip
11/25/2004	US20040233709 MRAM having memory cell array in which cross-point memory cells are arranged by hierarchical bit line scheme and data read method thereof
11/25/2004	US20040233708 Asymmetric memory cell
11/25/2004	US20040233706 Variable refresh control for a memory
11/25/2004	US20040233705 Random access memory device utilizing a vertically oriented select transistor
11/25/2004	US20040233703 Flash memory device having column predecoder capable of selecting all column selection transistors and stress test method thereof
11/25/2004	US20040233701 Programmable logic devices with stabilized configuration cells for reduced soft error rates
11/25/2004	US20040233700 Register controlled DLL for reducing current consumption
11/25/2004	US20040233696 Nonvolatile ferroelectric memory device having multi-bit control function
11/25/2004	US20040233695 Register array having timing reference sensing function, FeRAM using the same, and sensing method using timing reference
11/25/2004	US20040233694 Single bit nonvolatile memory cell and methods for programming and erasing thereof
11/25/2004	US20040233253 Closure member for an ink passage in an ink jet printhead
11/25/2004	US20040233252 Ink jet printhead
11/25/2004	US20040233251 Ink jet printhead chip with planar actuators
11/25/2004	US20040232974 Voltage generating circuit
11/25/2004	US20040232567 Semiconductor integrated circuit
11/25/2004	US20040232460 Magnetic random access memory and a method for manufacturing thereof
11/25/2004	US20040232458 Ferroelectric memory and method of fabricating the same
11/25/2004	US20040232457 Memory architecture with series grouped by cells
11/25/2004	US20040232451 Semiconductor storage device
11/25/2004	EP1620859A2 Reference current generator, and method of programming, adjusting and/or operating same
11/25/2004	DE10345522A1 ROM component with memory cells containing nanowires of electric conductivity, or with PN-junction, with latter comprising different current flow directions
11/25/2004	DE10319158A1 Flexible deactivation of row memory lines in dynamic memory components, especially RLDRAM components, whereby a device is used to selectively delay deactivation of a memory row address
11/25/2004	DE10318771A1 Integrated memory circuit with redundancy circuit for replacing memory area with address by redundant memory area has deactivation memory element for enabling/inhibiting replacement of memory area
11/25/2004	DE102004021076A1 Vorrichtung und Verfahren zur Mehrfachpegelabtastung in einem Speicherfeld Apparatus and method for multi-level scanning in a memory array
11/25/2004	DE102004014386A1 Spannungsgeneratorschaltung und zugehöriges Verfahren zur Spannungserzeugung Voltage generator circuit and associated method for generating voltage
11/24/2004	EP1480226A2 MRAM having memory cell array in which cross-point memory cells are arranged by hierarchical bit line scheme and data read method thereof
11/24/2004	EP1480225A2 Asymmetric memory cell
11/24/2004	EP1479060A1 Compact display assembly
11/24/2004	EP1479006A1 A memory and an adaptive timing system for controlling access to the memory
11/24/2004	CN1550018A Compensation of a bias magnetic field in a storage surface of a magnetoresistive storage cell
11/24/2004	CN1550017A MRAM with midpoint generator reference
11/24/2004	CN1549272A Power-saving static storage device control circuit
11/24/2004	CN1549121A Hiding error detecting/correcting latency in dynamic random access memory (DRAM)
11/24/2004	CN1177326C MRAM device
11/23/2004	US6823407 Output data path capable of multiple data rates
11/23/2004	US6822924 Synchronous semiconductor memory device having clock synchronization circuit and circuit for controlling on/off of clock tree of the clock synchronization circuit
11/23/2004	US6822923 RAM memory circuit and method for controlling the same
11/23/2004	US6822922 Clock synchronous circuit
11/23/2004	US6822920 SRAM-compatible memory device employing DRAM cells
11/23/2004	US6822919 Single ended output sense amplifier circuit with reduced power consumption and noise
11/23/2004	US6822918 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
11/23/2004	US6822917 Data write circuit in memory system and data write method
11/23/2004	US6822916 Read/write amplifier having vertical transistors for a DRAM memory
11/23/2004	US6822915 Method and circuit for charging a signal voltage through a semiconductor memory device
11/23/2004	US6822912 Semiconductor device
11/23/2004	US6822910 Non-volatile memory and operating method thereof
11/23/2004	US6822909 Method of controlling program threshold voltage distribution of a dual cell memory device
11/23/2004	US6822906 Sense amplifier structure for multilevel non-volatile memory devices and corresponding reading method
11/23/2004	US6822903 Apparatus and method for disturb-free programming of passive element memory cells
11/23/2004	US6822898 Multi-value nonvolatile semiconductor memory device
11/23/2004	US6822897 Thin film magnetic memory device selecting access to a memory cell by a transistor of a small gate capacitance
11/23/2004	US6822896 Magnetic random access memory
11/23/2004	US6822895 Magnetic memory device
11/23/2004	US6822894 Single event upset in SRAM cells in FPGAs with leaky gate transistors
11/23/2004	US6822892 Resistive memory element sensing using averaging
11/23/2004	US6822891 Ferroelectric memory device
11/23/2004	US6822890 Methods for storing data in non-volatile memories
11/23/2004	US6822889 Read only memory (ROM) and method for forming the same
11/23/2004	US6822888 Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric
11/23/2004	US6822887 Semiconductor circuit device with mitigated load on interconnection line
11/23/2004	US6822493 Voltage detection circuit, power-on/off reset circuit, and semiconductor device
11/23/2004	US6822335 Method for arranging wiring line including power reinforcing line and semiconductor device having power reinforcing line

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