Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
11/2005
11/24/2005US20050259500 Semiconductor memory device and semiconductor device
11/24/2005US20050259499 Semiconductor memory device having a global data bus
11/24/2005US20050259498 Asymmetrical programming mechanism for non-volatile memory
11/24/2005US20050259493 Method and system for controlling refresh in volatile memories
11/24/2005US20050259492 Semiconductor memory device and memory system
11/24/2005US20050259489 Semiconductor memory device
11/24/2005US20050259479 Semiconductor memory device and signal processing system
11/24/2005US20050259478 Memory device including self-ID information
11/24/2005US20050259477 Multi-port memory device
11/24/2005US20050259475 Ballistic injection nrom flash memory
11/24/2005US20050259474 Method for programming single-bit storage sonos type memory
11/24/2005US20050259471 Reference sensing circuit
11/24/2005US20050259470 Reference sensing circuit
11/24/2005US20050259469 System and method for destructive purge of memory device
11/24/2005US20050259464 Magnetic random access memory
11/24/2005US20050259463 Multi-bit magnetic random access memory device
11/24/2005US20050259462 SRAM circuitry
11/24/2005US20050259461 Ferroelectric memory and method for reading data from the ferroelectric memory
11/24/2005US20050258469 Magnetic memory with self-aligned magnetic keeper structure
11/24/2005US20050258248 Device which processes images in accordance with coded data on card
11/24/2005DE69034191T2 EEPROM-System mit aus mehreren Chips bestehender Blocklöschung EEPROM system with an existing block of several chips deletion
11/24/2005DE19928767B4 Halbleiterspeicherbauelement The semiconductor memory device
11/24/2005DE102005020973A1 Synchronous dynamic random access memory device signals generation of new refresh row when refresh operations are addressed to current refresh row in each memory cell array bank
11/24/2005DE102005018640A1 Schaltungsmodul Circuit module
11/24/2005DE102005016299A1 Tastverhältniskorrektur Tastverhältniskorrektur
11/24/2005DE102004059750A1 Siliziumspeichermedium, Steuereinheit und Steuerverfahren hiervon und ein auf einem Datenframe basierendes Speichermedium Silicon storage media controller and control method thereof, and a work based on a data storage medium frame
11/24/2005DE102004024942B3 Speicherschaltung und Verfahren zum Auslesen von einer in der Speicherschaltung enthaltenen spezifischen Betriebsinformationen Memory circuit and method for reading from a memory circuit included in the specific operation information
11/24/2005DE102004021694A1 Verfahren und Schaltungsanordnung zum Steuern eines Schreibzugriffs auf einen Halbleiterspeicher Method and circuit for controlling write access to a semiconductor memory
11/24/2005DE102004021398A1 Verfahren und Schaltungsanordnung zum Zurücksetzen einer integrierten Schaltung Method and circuit for resetting an integrated circuit
11/24/2005DE102004020576A1 Datenverarbeitungsvorrichtung mit schaltbarer Ladungsneutralität und Verfahren zum Betreiben einer Dual-Rail-Schaltungskomponente A data processing apparatus with switchable charge neutrality and method for operating a dual-rail circuit component
11/23/2005EP1598865A1 Mram with a novel buffer layer
11/23/2005EP1598834A2 Nanomagnetic materials
11/23/2005EP1598830A2 Semiconductor memory device and memory system
11/23/2005EP1598829A1 Semiconductor memory
11/23/2005EP1598805A2 SRAM core cell for light-emitting display
11/23/2005EP0917153B1 Semiconductor memory device
11/23/2005CN1701443A Magnetic storage device using ferromagnetic tunnel junction element
11/23/2005CN1701388A Multilevel cell memory architecture
11/23/2005CN1701387A Semiconductor memory device
11/23/2005CN1701386A Method for reading a passive matrix-addressable device and a device for performing the method
11/23/2005CN1701383A Non-volatile memory and method with reduced bit line crosstalk errors
11/23/2005CN1701377A Recording control device and method, program, and recording medium
11/23/2005CN1701306A Data transmission method and system
11/23/2005CN1700473A Ferroelectric memory and method for reading data from the ferroelectric memory
11/23/2005CN1700357A Semiconductor memory device for build-in fault diagnosis
11/23/2005CN1700356A Semiconductor memory
11/23/2005CN1700355A Worldline decoder and memory device
11/23/2005CN1700354A Sense amplifier and method for generating variable reference level
11/23/2005CN1700353A Memory device having delay locked loop
11/23/2005CN1700352A Semiconductor memory device and memory system
11/23/2005CN1700351A 半导体存储器 Semiconductor memory
11/23/2005CN1700350A Semiconductor storage
11/23/2005CN1700349A Silicon storage medium, controller used thereby, data write-in method and data reading method
11/23/2005CN1228848C Electronic circuit and semiconductor memory
11/23/2005CN1228847C Semiconductor integrated circuit device
11/22/2005US6968436 Memory controller that controls supply timing of read data
11/22/2005US6967897 FeRAM having wide page buffering function
11/22/2005US6967896 Address scramble
11/22/2005US6967895 Clock generation circuit and semiconductor memory device using the same
11/22/2005US6967893 Integrated synchronous memory and memory configuration having a memory module with at least one synchronous memory
11/22/2005US6967891 Information processing apparatus and semiconductor memory
11/22/2005US6967887 Semiconductor memory device including a double-gate dynamic random access memory cell having reduced current leakage
11/22/2005US6967886 Pseudo static random access memory and data refresh method thereof
11/22/2005US6967885 Concurrent refresh mode with distributed row address counters in an embedded DRAM
11/22/2005US6967884 RRAM circuit with temperature compensation
11/22/2005US6967883 Sense amplifier with reduced detection error
11/22/2005US6967882 Semiconductor memory including static memory
11/22/2005US6967879 Memory trouble relief circuit
11/22/2005US6967877 Temperature detecting circuit for controlling a self-refresh period of a semiconductor memory device
11/22/2005US6967876 Method for controlling programming voltage levels of non-volatile memory cells, the method tracking the cell features, and corresponding voltage regulator
11/22/2005US6967875 Static random access memory system with compensating-circuit for bitline leakage
11/22/2005US6967874 Non-volatile semiconductor memory device and electric device with the same
11/22/2005US6967872 Method and system for programming and inhibiting multi-level, non-volatile memory cells
11/22/2005US6967871 Reference sensing circuit
11/22/2005US6967870 Combination NAND-NOR memory device
11/22/2005US6967868 Semiconductor memory device having flexible column redundancy scheme
11/22/2005US6967867 Semiconductor memory device and method for correcting memory cell data
11/22/2005US6967866 Semiconductor memory and semiconductor integrated circuit
11/22/2005US6967865 Low-current and high-speed phase-change memory devices and methods of driving the same
11/22/2005US6967864 Semiconductor memory device including magneto resistive element and method of fabricating the same
11/22/2005US6967863 Perpendicular magnetization magnetic element utilizing spin transfer
11/22/2005US6967862 Semiconductor memory device with magnetic disturbance reduced
11/22/2005US6967861 Method and apparatus for improving cycle time in a quad data rate SRAM device
11/22/2005US6967860 Ferroelectric memory device and control method thereof
11/22/2005US6967859 Ferroelectric memory configuration having successively connected ferroelectric capacitor coupling to the gate of a read transistor and different bias voltages applied in read/write/erase
11/22/2005US6967858 Nonvolatile ferroelectric memory device and method for storing multiple bit using the same
11/22/2005US6967553 Planar inductive element
11/22/2005US6967366 Magnetoresistive random access memory with reduced switching field variation
11/22/2005US6967358 Thyristor-type memory device
11/17/2005WO2005109516A1 Split-channel antifuse array architecture
11/17/2005WO2005109443A1 Non-volatile memory and control with improved partial page program capability
11/17/2005WO2005109441A1 Semiconductor device and writing method
11/17/2005WO2005109439A1 Nonvolatile semiconductor memory, semiconductor device and charge pump circuit
11/17/2005WO2005109437A2 Pfet nonvolatile memory
11/17/2005WO2005109436A2 Charge pump clock for non-volatile memories
11/17/2005WO2005024905A3 Method of writing to a multi-state magnetic random access memory cell
11/17/2005WO2004095515A8 Methods for contracting conducting layers overlying magnetoelectronic elements of mram devices
11/17/2005US20050256997 Methods of sanitizing a flash-based data storage device
11/17/2005US20050255665 Manufacturing method of a contact structure and phase change memory cell with elimination of double contacts
11/17/2005US20050254337 Latency control circuit and method of latency control
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