| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
|---|
| 01/04/2006 | CN1717743A Method and device for improved magnetic field generation during a write operation of a magnetoresistive memory device |
| 01/04/2006 | CN1717742A Current re-routing scheme for serial-programmed MRAM |
| 01/04/2006 | CN1717741A Sense amplifier for a memory having at least two distinct resistance states |
| 01/04/2006 | CN1717662A Memory module, memory system, and information device |
| 01/04/2006 | CN1716613A Memory device and its producing method |
| 01/04/2006 | CN1716608A Memory gain cells and method for producing the same |
| 01/04/2006 | CN1716454A Flash memory device including bit line voltage clamp circuit for controlling bit line voltage during programming, and bit line voltage control method thereof |
| 01/04/2006 | CN1716453A Multi-port memory device for buffering between hosts and non-volatile memory devices |
| 01/04/2006 | CN1716448A High speed low power consumption current sensitive amplifier |
| 01/04/2006 | CN1716447A Semiconductor memory device for low power consumption |
| 01/04/2006 | CN1716446A Input/output circuit |
| 01/04/2006 | CN1716445A Semiconductor memory device and semiconductor integrated circuit |
| 01/04/2006 | CN1716444A Semiconductor memory device capable of stably setting mode register set and method therefor |
| 01/04/2006 | CN1716443A Semiconductor memory device and error correction method thereof |
| 01/04/2006 | CN1716442A Memory device |
| 01/04/2006 | CN1235229C Voltage hoisting circuit with no affect of bulk effect |
| 01/04/2006 | CN1235228C Bit line controlling decoder circuit, semiconductor storage device and data reading method thereof |
| 01/04/2006 | CN1235158C Dynamic latch receiver with automatic reset pointer |
| 01/04/2006 | CN1235152C Semiconductor device and driving method of semiconductor device |
| 01/03/2006 | US6983388 Method and apparatus for reducing leakage power in a cache memory by using a timer control signal that removes power to associated cache lines |
| 01/03/2006 | US6983010 High frequency equalizer using a demultiplexing technique and related semiconductor device |
| 01/03/2006 | US6982924 Data output control circuit |
| 01/03/2006 | US6982923 Semiconductor memory device adaptive for use circumstance |
| 01/03/2006 | US6982921 Multiple configuration multiple chip memory device and method |
| 01/03/2006 | US6982920 Flash array implementation with local and global bit lines |
| 01/03/2006 | US6982918 Data storage device and refreshing method for use with such device |
| 01/03/2006 | US6982917 DRAM partial refresh circuits and methods |
| 01/03/2006 | US6982916 Method and system for providing temperature dependent programming for magnetic memories |
| 01/03/2006 | US6982915 SRAM with temperature-dependent voltage control in sleep mode |
| 01/03/2006 | US6982914 Semiconductor memory device |
| 01/03/2006 | US6982912 Semiconductor memory device |
| 01/03/2006 | US6982910 Reverse voltage generation circuit |
| 01/03/2006 | US6982909 System and method for reading a memory cell |
| 01/03/2006 | US6982908 Magnetic random access memory device capable of providing a constant current to a reference cell |
| 01/03/2006 | US6982903 Field effect devices having a source controlled via a nanotube switching element |
| 01/03/2006 | US6982902 MRAM array having a segmented bit line |
| 01/03/2006 | US6982901 Memory device and method of use |
| 01/03/2006 | US6982900 Semiconductor integrated circuit device |
| 01/03/2006 | US6982899 Semiconductor memory device |
| 01/03/2006 | US6982898 Molecular memory integrated circuit utilizing non-vibrating cantilevers |
| 01/03/2006 | US6982897 Nondestructive read, two-switch, single-charge-storage device RAM devices |
| 01/03/2006 | US6982896 Nonvolatile ferroelectric memory device having a multi-bit control function |
| 01/03/2006 | US6982895 Method for reading a passive matrix-addressable device and a device for performing the method |
| 01/03/2006 | US6982894 Three-dimensional magnetic memory array with a minimal number of access conductors therein and methods thereof |
| 01/03/2006 | US6982893 Memory module having a plurality of integrated memory components |
| 01/03/2006 | US6982892 Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules |
| 01/03/2006 | US6982450 Magnetoresistive memory devices |
| 01/03/2006 | US6982449 Junction-isolated depletion mode ferroelectric memory devices |
| 01/03/2006 | US6982446 Nonvolatile magnetic memory device and manufacturing method thereof |
| 01/03/2006 | US6982445 MRAM architecture with a bit line located underneath the magnetic tunneling junction device |
| 12/29/2005 | WO2005124786A1 Semiconductor memory |
| 12/29/2005 | WO2005124785A1 Temperature detector for semiconductor apparatus and semiconductor memory |
| 12/29/2005 | WO2005124558A2 Method and system for optimizing the number of word line segments in a segmented mram array |
| 12/29/2005 | WO2005123392A1 System for aligning a charge tunnel of an ink jet printer |
| 12/29/2005 | WO2005123235A1 Method and system for providing common read and write word lines for a segmented word line mram array |
| 12/29/2005 | WO2005096313A3 Separate write and read access architecture for magnetic tunnel junction |
| 12/29/2005 | WO2005082061A3 Spin transfer magnetic element with free layers having high perpendicular anisotropy and in-plane equilibrium magnetization |
| 12/29/2005 | WO2005081769A3 Nor-type channel-program channel-erase contactless flash memory on soi |
| 12/29/2005 | US20050289444 Low power cost-effective ECC memory system and method |
| 12/29/2005 | US20050289442 Error correction in ROM embedded DRAM |
| 12/29/2005 | US20050289424 Error correction in ROM embedded DRAM |
| 12/29/2005 | US20050289410 Internal signal test device and method thereof |
| 12/29/2005 | US20050289293 Dual-port DRAM cell with simultaneous access |
| 12/29/2005 | US20050289260 One button external backup |
| 12/29/2005 | US20050287736 Latch-up prevention for memory cells |
| 12/29/2005 | US20050286339 Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM |
| 12/29/2005 | US20050286336 Flash EEprom system |
| 12/29/2005 | US20050286331 Semiconductor memory device |
| 12/29/2005 | US20050286330 Semiconductor memory device |
| 12/29/2005 | US20050286329 Memory device |
| 12/29/2005 | US20050286323 Semiconductor memory device and circuit layout of dummy cell |
| 12/29/2005 | US20050286321 Probe storage device |
| 12/29/2005 | US20050286315 Methods for erasing flash memory |
| 12/29/2005 | US20050286314 Methods for erasing flash memory |
| 12/29/2005 | US20050286313 Methods for erasing flash memory |
| 12/29/2005 | US20050286310 Charge pump circuitry having adjustable current outputs |
| 12/29/2005 | US20050286309 Bit refresh circuit for refreshing register bit values, integrated circuit device having the same, and method of refreshing register bit values |
| 12/29/2005 | US20050286308 Non-volatile semiconductor memory device |
| 12/29/2005 | US20050286307 Data line driver capable of generating fixed gradation voltage without switches |
| 12/29/2005 | US20050286306 Flash memory file system with transacted operations |
| 12/29/2005 | US20050286305 Sensing circuit for flash memory device operating at low power supply voltage |
| 12/29/2005 | US20050286304 Flash memory with coarse/fine gate step programming |
| 12/29/2005 | US20050286302 Flash memory device including bit line voltage clamp circuit for controlling bit line voltage during programming, and bit line voltage control method thereof |
| 12/29/2005 | US20050286301 Semiconductor memory device |
| 12/29/2005 | US20050286300 Non-contiguous address erasable blocks and command in flash memory |
| 12/29/2005 | US20050286299 Flash memory and program verify method for flash memory |
| 12/29/2005 | US20050286298 Operating a storage component |
| 12/29/2005 | US20050286297 Multiple level cell memory device with single bit per cell, re-mappable memory block |
| 12/29/2005 | US20050286295 Memory cell array latchup prevention |
| 12/29/2005 | US20050286294 Resistance variable memory elements based on polarized silver-selenide network growth |
| 12/29/2005 | US20050286293 Horizontal memory gain cells |
| 12/29/2005 | US20050286292 Semiconductor device and method for fabricating the same |
| 12/29/2005 | US20050286291 Dual access DRAM |
| 12/29/2005 | US20050286290 Ferroelectric material for perroelectric devices |
| 12/29/2005 | US20050286289 Ferroelectric memory device |
| 12/29/2005 | US20050286288 Latch-up prevention for memory cells |
| 12/29/2005 | US20050286287 Complementary nonvolatile memory device, methods of operating and manufacturing the same, logic device and semiconductor device including the same, and reading circuit for the same |
| 12/29/2005 | US20050286285 Semiconductor memory device and method of arranging signal and power lines thereof |
| 12/29/2005 | US20050286284 Method and system for expanding flash storage device capacity |
| 12/29/2005 | US20050285650 Fast bistable circuit protected against random events |