Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
12/2005
12/22/2005US20050281075 Semiconductor storage device
12/22/2005US20050281074 Input return path based on VDDQ/VSSQ
12/22/2005US20050281073 Phase-change memory element driver circuits using measurement to control current and methods of controlling drive current of phase-change memory elements using measurement
12/22/2005US20050281072 Non-volatile, high-density integrated circuit memory
12/22/2005US20050281071 Word line driver circuits for use in semiconductor memory and driving method thereof
12/22/2005US20050281070 Ferroelectric memory device, electronic apparatus
12/22/2005US20050281069 Computer systems, processes for turning a SRAM cell off, and processes for writing a SRAM cell
12/22/2005US20050280960 Magnetic random access memory array with coupled soft adjacent magnetic layer
12/22/2005US20050280479 Circuits and methods of temperature compensation for refresh oscillator
12/22/2005US20050280465 Internal power supply voltage generation circuit that can suppress reduction in internal power supply voltage in neighborhood of lower limit region of external power supply voltage
12/22/2005US20050280070 Semiconductor memory device and method of manufacturing the same
12/22/2005US20050280043 Magnetoresistive element and magnetic memory
12/22/2005US20050280028 Semiconductor device
12/22/2005US20050280023 Gated lateral thyristor-based random access memory cell (GLTRAM)
12/22/2005US20050280000 Semiconductor memory device
12/22/2005DE4426841B4 Signalübertragungseinrichtung Signal transmission device
12/22/2005DE19910899B4 Dynamische Halbleiterspeichervorrichtung mit niedrigem Stromverbrauchsmodus Dynamic semiconductor memory device with low power consumption mode
12/22/2005DE112004000152T5 Magnetspeicher, Schreibstrom-Treiberschaltung und Schreibstrom-Treiberverfahren Magnetic memory write current and write current driver circuit driving method
12/22/2005DE102005026663A1 Nichtflüchtiges Speicherbauelement mit ISPP Non-volatile memory device with ISPP
12/22/2005DE102004026110A1 Semiconductor memory used in semiconductor switching devices comprises an arrangement having storage material formed as a number of molecules arranged between a first lower electrode and a second upper electrode
12/22/2005DE102004025900A1 Leselatenz-Steuerschaltung Read latency control circuit
12/22/2005DE102004025702A1 Process for the dynamic configuration of electronic circuits uses control and address inputs to a control circuit
12/22/2005DE10158795B4 Magnetoresistive Speicherzelle mit dynamischer Referenzschicht Magnetoresistive memory cell with dynamic reference layer
12/22/2005DE10001940B4 Direktzugriffsspeicherbauelement Random access memory device
12/21/2005EP1608018A2 Semiconductor device, methods of operating and manufacturing
12/21/2005EP1607980A2 A novel capping structure for enhancing dR/R of the MTJ device
12/21/2005EP1607979A2 Memory architecture with segmented write lines
12/21/2005EP1606821A2 An apparatus and method for a configurable mirror fast sense amplifier
12/21/2005EP1606820A1 Sense amplifier systems and a matrix-addressable memory device provided therewith
12/21/2005EP1606215A2 Nanoscopic structure and devices using the same
12/21/2005EP1516307B1 Mram in-pixel memory for display devices
12/21/2005EP1456852A4 Method and system for programming and inhibiting multi-level, non-volatile memory cells
12/21/2005EP1435101B1 Spin-valve magnetoresistive device with enhanced performance
12/21/2005EP1305795A4 All metal giant magnetoresistive memory
12/21/2005CN1710665A Shared decoupling capacitance
12/21/2005CN1710664A Method for prolonging use time of portable device through controlling memory
12/21/2005CN1710663A Ferroelectric memory device, electronic apparatus
12/21/2005CN1710519A Self-refreshing electricity consumption method of saving SDRAM through spare data
12/21/2005CN1232986C Internal voltage level control circuit and semiconductor memory device and their control method
12/21/2005CN1232985C Magnetic random access storage and method of writing and reading data
12/20/2005US6978402 Semiconductor memory
12/20/2005US6977865 Method and circuit for controlling operation mode of PSRAM
12/20/2005US6977864 Synchronous dynamic random access memory device with single data rate/double data rate mode
12/20/2005US6977860 SRAM power reduction
12/20/2005US6977859 Semiconductor memory device and control method thereof
12/20/2005US6977858 Semiconductor device
12/20/2005US6977857 DRAM and refresh method thereof
12/20/2005US6977856 Semiconductor integrated circuit device operating at high speed and low power consumption
12/20/2005US6977848 Data output control circuit
12/20/2005US6977842 Boosted substrate/tub programming for flash memories
12/20/2005US6977839 Magnetic memory storage device
12/20/2005US6977838 Method and system for providing a programmable current source for a magnetic memory
12/20/2005US6977837 Semiconductor memory including static random access memory formed of FinFET
12/20/2005US6977835 Ferroelectric register, and method for manufacturing capacitor of the same
12/20/2005US6977834 Semiconductor integrated circuit device
12/20/2005US6977832 Semiconductor memory device capable of improving quality of voltage waveform given in a signal interconnection layer
12/20/2005US6977655 Dual mode DDR SDRAM/SGRAM
12/20/2005US6977402 Memory device having storage part and thin-film part
12/20/2005US6977401 Magnetic memory device having magnetic shield layer, and manufacturing method thereof
12/20/2005US6977389 Planar polymer memory device
12/20/2005US6976751 Motion transmitting structure
12/20/2005CA2269857C Memory element with energy control mechanism
12/15/2005WO2005119783A2 Ballistic injection nrom flash memory
12/15/2005WO2005119695A2 Memory device with user configurable density/performance
12/15/2005WO2005119693A2 Configurable ready/busy control
12/15/2005WO2005119692A1 Method and system for providing seamless self-refresh for directed bank refresh in volatile memories
12/15/2005WO2005119691A1 Method and system for providing directed bank refresh for volatile memories
12/15/2005WO2005119690A1 Method and system for providing independent bank refresh for volatile memories
12/15/2005WO2005119689A1 A magnetic memory device
12/15/2005WO2005119688A1 Sense amplifying magnetic tunnel device
12/15/2005WO2005119687A2 Automatic hidden refresh in a dram and method therefor
12/15/2005WO2005119686A2 Method of increasing ddr memory bandwidth in ddr sdram modules
12/15/2005WO2005119456A1 Cache line memory and method therefor
12/15/2005WO2005024834A3 Low voltage operation dram control circuits
12/15/2005US20050278596 Semiconductor integrated circuit device
12/15/2005US20050278594 Semiconductor memory device having ECC circuit
12/15/2005US20050278592 Semiconductor memory
12/15/2005US20050278490 Memory access control apparatus and method of controlling memory access
12/15/2005US20050278474 Method of increasing DDR memory bandwidth in DDR SDRAM modules
12/15/2005US20050277207 Mask schemes for patterning magnetic tunnel junctions
12/15/2005US20050277206 Structure and method of patterning a magnetic tunnel junction stack for a magneto-resistive random access memory
12/15/2005US20050276149 Method of manipulating a quantum system comprising a magnetic moment
12/15/2005US20050276148 Semiconductor storage device interrupt control circuit
12/15/2005US20050276146 Semiconductor memory device
12/15/2005US20050276144 Temperature detector providing multiple detected temperature points using single branch and method of detecting shifted temperature
12/15/2005US20050276142 Automatic hidden refresh in a dram and method therefor
12/15/2005US20050276141 Memory with serial input/output terminals for address and data and method therefor
12/15/2005US20050276140 Semiconductor memory
12/15/2005US20050276139 DRAM device with a refresh period that varies responsive to a temperature signal having a hysteresis characteristic
12/15/2005US20050276138 Semiconductor memory device
12/15/2005US20050276134 Memory device
12/15/2005US20050276128 Redundancy circuits and memory devices having a twist bitline scheme and methods of repairing defective cells in the same
12/15/2005US20050276127 Semiconductor integrated circuit device having power supply startup sequence
12/15/2005US20050276122 Efficient recovery of failed memory cell
12/15/2005US20050276120 Erase algorithm for multi-level bit flash memory
12/15/2005US20050276119 Memory block erasing in a flash memory device
12/15/2005US20050276117 Ballistic direct injection flash memory cell on strained silicon structures
12/15/2005US20050276116 Nonvolatile semiconductor memory, a data write-in method for the nonvolatile semiconductor memory and a memory card
12/15/2005US20050276111 Memory device capable of stable data writing
12/15/2005US20050276110 Nonvolatile memory apparatus
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