Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
06/2006
06/14/2006DE10031947B4 Schaltungsanordnung zum Ausgleich unterschiedlicher Spannungen auf Leitungszügen in integrierten Halbleiterschaltungen Circuitry to compensate for different voltages on line trains in semiconductor integrated circuits
06/14/2006CN1788321A Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM
06/14/2006CN1787249A Sulfur compound random access internal memory and mfg. method thereof
06/14/2006CN1787224A Memory cell mfg.method,memory cell and phase-change memory cell
06/14/2006CN1787110A Method and apparatus for realizing interface
06/14/2006CN1787109A Method for controlling data flowing of high speed memory body
06/14/2006CN1787107A Inner storage voltage supply circuit with protecting circuit
06/13/2006US7061828 Fully-hidden refresh dynamic random access memory
06/13/2006US7061827 Semiconductor memory device
06/13/2006US7061821 Address wrap function for addressable memory devices
06/13/2006US7061820 Voltage keeping scheme for low-leakage memory devices
06/13/2006US7061819 Memory device
06/13/2006US7061818 Memory and refresh method for memory
06/13/2006US7061814 Semiconductor device realized by using partial SOI technology
06/13/2006US7061807 Semiconductor memory device
06/13/2006US7061806 Floating-body memory cell write
06/13/2006US7061804 Robust and high-speed memory access with adaptive interface timing
06/13/2006US7061803 Method and device for preserving word line pass bias using ROM in NAND-type flash memory
06/13/2006US7061800 Nonvolatile semiconductor memory device having improved redundancy relieving rate
06/13/2006US7061799 Nonvolatile semiconductor memory device
06/13/2006US7061798 Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
06/13/2006US7061797 Hybrid memory cell for spin-polarized electron current induced switching and writing/reading process using such memory cell
06/13/2006US7061796 Thin film magnetic memory device for programming required information with an element similar to a memory cell information programming method
06/13/2006US7061795 Magnetic random access memory device
06/13/2006US7061794 Wordline-based source-biasing scheme for reducing memory cell leakage
06/13/2006US7061793 Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices
06/13/2006US7061792 Low AC power SRAM architecture
06/13/2006US7061791 High density molecular memory device
06/13/2006US7061790 Semiconductor memory device and data write method
06/13/2006US7061789 Sensing scheme for programmable resistance memory using voltage coefficient characteristics
06/13/2006US7061788 Semiconductor storage device
06/13/2006US7061787 Field ramp down for pinned synthetic antiferromagnet
06/13/2006US7061786 Semiconductor memory device and memory system
06/13/2006US7061784 Semiconductor memory module
06/13/2006US7061485 Method and system for producing a model from optical images
06/13/2006US7061306 Voltage booster
06/13/2006US7061053 Semiconductor element and semiconductor memory device using the same
06/13/2006US7061040 Memory device
06/13/2006US7061036 Magnetic random access memory and a method for manufacturing thereof
06/13/2006US7061034 Magnetic random access memory including middle oxide layer and method of manufacturing the same
06/13/2006US7061007 Ferromagnetic fractal combination structure
06/13/2006US7060194 Dry etching method for magnetic material
06/13/2006US7059533 Authentication using a read-once memory
06/13/2006CA2466682C A matrix-addressable optoelectronic apparatus and electrode means in the same
06/13/2006CA2202692C Column redundancy in semiconductor memories
06/08/2006WO2006059641A1 Magnetic memory
06/08/2006WO2006059559A1 Magnetic random access memory, operation method thereof, and manufacturing method thereof
06/08/2006WO2006059379A1 Semiconductor device employing dynamic circuit
06/08/2006WO2006011982B1 Circuit for preventing latch-up in cmos memory cell
06/08/2006WO2005098864A3 Circuit for accessing a chalcogenide memory array
06/08/2006US20060123222 Techniques for storing accurate operating current values
06/08/2006US20060123221 Techniques for storing accurate operating current values
06/08/2006US20060121674 Method of making a scalable flash EEPROM memory cell with notched floating gate and graded source region
06/08/2006US20060121670 Memory device having a semiconducting polymer film
06/08/2006US20060120242 Information reproducing method judging a multivalued level of a present cell by referring to judged multivalued levels of a preceding cell and an ensuing cell
06/08/2006US20060120198 Nonvolatile memory
06/08/2006US20060120194 EEPROM device having selecting transistors and method fabricating the same
06/08/2006US20060120187 Method and apparatus for semiconductor device repair with reduced number of programmable elements
06/08/2006US20060120180 Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information
06/08/2006US20060120166 Data processing apparatus and method for flash memory
06/08/2006US20060120165 Faster programming of higher level states in multi-level cell flash memory
06/08/2006US20060120164 Nonvolatile memory system, semiconductor memory, and writing method
06/08/2006US20060120162 Method of writing data to a semiconductor memory device
06/08/2006US20060120161 Programming method of multilevel memories and corresponding circuit
06/08/2006US20060120160 Display device
06/08/2006US20060120156 Nonvolatile semiconductor memory device
06/08/2006US20060120155 Nonvolatile semiconductor memory
06/08/2006US20060120154 Structure for testing nand flash memory and method of testing nand flash memory
06/08/2006US20060120153 System and method for over erase reduction of nitride read only memory
06/08/2006US20060120150 Thin-film magnetic memory device with memory cells having magnetic tunnel junction
06/08/2006US20060120149 Magnetic memory array
06/08/2006US20060120148 Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell
06/08/2006US20060120147 Magnetic Memory Array
06/08/2006US20060120146 Magnetic memory device, sense amplifier circuit and method of reading from magnetic memory device
06/08/2006US20060120145 Magnetic memory device and method of reading the same
06/08/2006US20060120144 Apparatus and method for small signal sensing in an sram cell utilizing pfet access devices
06/08/2006US20060120143 SRAM cell design with high resistor CMOS gate structure for soft error rate improvement
06/08/2006US20060120142 Semiconductor memory device
06/08/2006US20060120141 Configuration memory structure
06/08/2006US20060120140 Atomic probes and media for high density data storage
06/08/2006US20060120139 Inputting and outputting operating parameters for an integrated semiconductor memory device
06/08/2006US20060120138 Semiconductor memory with volatile and non-volatile memory cells
06/08/2006US20060120137 Apparatus and method for memory efficient, programmable, pattern matching finite state machine hardware
06/08/2006US20060120136 Shared address lines for crosspoint memory
06/08/2006US20060120135 Semiconductor memory device
06/08/2006US20060120134 Ferroelectric memory
06/08/2006US20060120128 Associative memory having a mask function for use in network devices and network system
06/08/2006US20060120126 Magnetic cell and magnetic memory
06/08/2006US20060120125 Semiconductor memory device and defect remedying method thereof
06/08/2006US20060119991 Method for reducing power consumption in a state retaining circuit, state retaining circuit and electronic device
06/08/2006US20060119665 Printer formed from integrated circuit printhead
06/08/2006US20060118856 Twin EEPROM memory transistors with subsurface stepped floating gates
06/08/2006US20060118849 Semiconductor memory device including an SOI
06/08/2006US20060118848 Microelectronic programmable device and methods of forming and programming the same
06/08/2006US20060118774 Multiple bit chalcogenide storage device
06/08/2006US20060118423 Tunable cantilever apparatus and method for making same
06/08/2006DE112004001501T5 Gesteuerte Substratspannung für Speicherschaltung Controlled substrate voltage for the memory circuit
06/08/2006DE102005009553B3 Trough capacitor plate is formed by preparing a semiconductor wafer, etching a trough for each storage cell, and precipitating a layer containing a dopant on the wafer
06/08/2006DE102004058612A1 Voltage supply circuit for integrated circuit especially a DRAM memory circuit has regulating circuit with on off switching to prevent voltage deviation from limiting value
06/08/2006DE102004058131A1 Data selecting method, involves activating sense amplifier to evaluate information of bit line and opening control unit to disconnect bit line by sense amplifier, and delivering selected information on data bus