Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
07/2008
07/17/2008WO2008011441A3 Method for configuring compensation for coupling between adjacent storage elements in a nonvolatile memory
07/17/2008WO2008005057A3 Partitioned random access and read only memory
07/17/2008US20080170444 Integrated circuit, memory chip and method of evaluating a memory state of a resistive memory cell
07/17/2008US20080170439 Multi-level memory
07/17/2008US20080170438 NAND Memory with Virtual Channel
07/17/2008US20080170432 Magnetic random access memory and write method of the same
07/17/2008US20080170431 Driving method and system for a phase change memory
07/17/2008US20080170430 Cmos sram/rom unified bit cell
07/17/2008US20080170429 Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same
07/17/2008US20080170428 Nonvolatile semiconductor memory device and method of writing into the same
07/17/2008US20080170427 Resistive random access memory devices and methods of manufacturing the same
07/17/2008US20080170424 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield
07/17/2008US20080168649 Magnetic recording element and method of manufacturing magnetic recording element
07/17/2008DE102007063215A1 Leseverstärkerschaltung, Halbleiterspeicherelement und Verfahren zum Betreiben eines Halbleiterspeicherelements A sense amplifier circuit, semiconductor memory device and method of operating a semiconductor memory device
07/17/2008DE10058227B4 Halbleiterspeicherbauelement, Durchlass-/Zwischenspeichereinheit hierfür und zugehöriges Datenübertragungsverfahren A semiconductor memory device, transmission / latch unit therefor, and associated data transfer process
07/16/2008EP1943651A1 Dynamic random access memory device and method for self-refreshing memory cells
07/16/2008EP1943184A1 Non-volatile memory device
07/16/2008EP1683160A4 A method circuit and system for read error detection in a non-volatile memory array
07/16/2008CN101223605A Memory control device
07/16/2008CN101222019A Electrolyte thin film (AgI)x(AgPO3)1-x based on amorphous solid and its preparing method
07/16/2008CN101221970A Phase-change memory device having phase change material pattern shared between adjacent cells and electronic product including the phase-change memory
07/16/2008CN101221953A Multiport and multi-channel embedded dynamic ram and operating method thereof
07/16/2008CN101221924A Ferroelectric memory devices having a protruding bottom electrode and methods of forming the same
07/16/2008CN101221811A Multi-bit resistive memory
07/16/2008CN101221808A Semiconductor memory device and sense amplifier circuit
07/16/2008CN101221807A Semiconductor memory device, sense amplifier circuit and memory cell reading method
07/16/2008CN101221532A Interface method for implementing dynamic RAM with data processing capability
07/16/2008CN100403450C Memory device with self-assembled polymer film and method of making the same
07/16/2008CN100403449C Synchronized semiconductor memory
07/16/2008CN100403448C Strong dielectric memory device and electronic device
07/16/2008CN100403447C MRAM write apparatus and method
07/16/2008CN100403446C Multiport scanning chain register device and method
07/16/2008CN100403445C MRAM with midpoint generator reference
07/16/2008CN100403444C Reluctance type random access memory circuit
07/16/2008CN100403204C Efficient current-feedback power supply and applications thereof
07/16/2008CN100403144C Thin film transistor array panel for display
07/16/2008CA2618261A1 A method and calculator for modeling non-equilibrium spin polarized charge transport in nano-structures
07/15/2008US7400544 Actively driven VREF for input buffer noise immunity
07/15/2008US7400543 Metal programmable self-timed memories
07/15/2008US7400539 Memory device having terminals for transferring multiple types of data
07/15/2008US7400538 NROM memory device with enhanced endurance
07/15/2008US7400537 Systems for erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells
07/15/2008US7400536 Memory system and a voltage regulator
07/15/2008US7400535 System that compensates for coupling during programming
07/15/2008US7400530 Semiconductor memory
07/15/2008US7400529 Non-volatile memory cell and non-volatile memory device using said cell
07/15/2008US7400528 Intergrated circuit for programming resistive memory cells
07/15/2008US7400526 Memory element, memory read-out element and memory cell
07/15/2008US7400525 Memory cell with independent-gate controlled access devices and memory using the cell
07/15/2008US7400524 Semiconductor memory device and semiconductor device
07/15/2008US7400523 8T SRAM cell with higher voltage on the read WL
07/15/2008US7400522 Resistance change memory device having a variable resistance element formed of a first and second composite compound for storing a cation
07/15/2008US7400521 Integrated circuit, memory chip and method of evaluating a memory state of a resistive memory cell
07/15/2008US7400034 Semiconductor device
07/15/2008US7400009 Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers
07/15/2008US7400006 Conductive memory device with conductive oxide electrodes
07/15/2008US7399678 Method for reading an array of multi-bit ROM cells with each cell having bi-directional read
07/15/2008US7398597 Method of fabricating monolithic microelectromechanical fluid ejection device
07/15/2008CA2352295C A method and a system for assisting a user in a medical self treatment, said self treatment comprising a plurality of actions
07/10/2008WO2008083214A1 Programming non-volatile memory with reduced program disturb by removing pre-charg dependency on word line data
07/10/2008WO2008083196A2 Margined neighbor reading for non-volatile memory read operations including coupling compensation
07/10/2008WO2008083162A1 Retention margin program verification
07/10/2008WO2008083137A1 Reading of a nonvolatile memory cell by taking account of the stored state of a neighboring memory cell
07/10/2008WO2008083131A2 Method for programming with initial programming voltage based on trial
07/10/2008WO2008082995A1 Reversible polarity decoder circuit and related methods
07/10/2008WO2008082852A1 Multibits resistance changing memory cell architecture and its writing method
07/10/2008WO2008082591A2 High speed interface for multi-level memory
07/10/2008WO2008082443A1 Memory storage devices comprising different ferromagnetic material layers, and methods of making and using the same
07/10/2008WO2008081426A1 Avoiding errors in a flash memory by using substitution transformations
07/10/2008WO2008080213A1 High speed otp sensing scheme
07/10/2008WO2008063972A3 Controlled boosting in non-volatile memory soft programming
07/10/2008WO2008028129A3 Non-volatile memory cell in standard cmos process
07/10/2008US20080168295 Data processing system and image processing system
07/10/2008US20080168227 Disk Array Optimizing The Drive Operation Time
07/10/2008US20080165645 Optical recording medium, recording/reproducing apparatus, and recording/reproducing method
07/10/2008US20080165639 Optical recording medium, recording/reproducing apparatus, and recording/reproducing method
07/10/2008US20080165638 Optical recording medium, recording/reproducing apparatus, and recording/reproducing method
07/10/2008US20080165637 Optical recording medium, recording/reproducing apparatus, and recording/reproducing method
07/10/2008US20080165636 Optical recording medium, recording/reproducing apparatus, and recording/reproducing method
07/10/2008US20080165606 Semiconductor memory device for reducing peak current during refresh operation
07/10/2008US20080165598 Bi-directional resistive random access memory capable of multi-decoding and method of writing data thereto
07/10/2008US20080165588 Reset method of non-volatile memory
07/10/2008US20080165587 Operating method of p-channel non-volatile memory
07/10/2008US20080165578 Method of operating multi-level cell
07/10/2008US20080165577 Semiconductor device
07/10/2008US20080165576 Memory storage devices comprising different ferromagnetic material layers, and methods of making and using the same
07/10/2008US20080165575 Memory cell array biasing method and a semiconductor memory device
07/10/2008US20080165574 Memory device including thermal conductor located between progammable volumes
07/10/2008US20080165573 Memory including two access devices per phase change element
07/10/2008US20080165572 Method, Apparatus and Computer Program Product for Stepped Reset Programming Process on Programmable Resistive Memory Cell
07/10/2008US20080165571 Method, Apparatus and Computer Program Product for Read Before Programming Process on Multiple Programmable Resistive Memory Cell
07/10/2008US20080165570 Current Compliant Sensing Architecture for Multilevel Phase Change Memory
07/10/2008US20080165569 Resistance Limited Phase Change Memory Material
07/10/2008US20080165568 Probes and Media for High Density Data Storage
07/10/2008US20080165567 Semiconductor memory device
07/10/2008US20080165566 Non-volatile memory including sub cell array and method of writing data thereto
07/10/2008US20080165565 Ferroelectric Thin Films and Devices Comprising Thin Ferroelectric Films
07/10/2008US20080165254 Camera Device Incorporating A Print Roll Validation Apparatus
07/10/2008US20080165253 Image sensing and printing device
07/10/2008US20080165226 Nozzle assembly having a sprung electromagnetically operated plunger