Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
05/2008
05/06/2008US7369456 DRAM memory with autoprecharge
05/06/2008US7369448 Input circuit for memory device
05/06/2008US7369442 Erase discharge method of memory device and discharge circuit performing the method
05/06/2008US7369441 Sensing circuit for multi-level flash memory
05/06/2008US7369438 Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications
05/06/2008US7369437 System for reading non-volatile storage with efficient setup
05/06/2008US7369435 Write once read only memory employing floating gates
05/06/2008US7369432 Method for implementing a counter in a memory with increased memory efficiency
05/06/2008US7369431 Method for initializing resistance-variable material, memory device containing a resistance-variable material, and method for initializing nonvolatile memory circuit including variable resistor
05/06/2008US7369430 Adaptive algorithm for MRAM manufacturing
05/06/2008US7369429 Non-volatile memory device having toggle cell
05/06/2008US7369428 Methods of operating a magnetic random access memory device and related devices and structures
05/06/2008US7369427 Magnetic elements with spin engineered insertion layers and MRAM devices using the magnetic elements
05/06/2008US7369426 Magnetoresistive memory cell with dynamic reference layer
05/06/2008US7369425 Method and system for DRAM sensing
05/06/2008US7369424 Programmable memory cell and operation method
05/06/2008US7369423 Nonvolatile memory device using hybrid switch cell
05/06/2008US7368298 Method of manufacturing ferroelectric semiconductor device
05/06/2008US7367729 Printer within a computer keyboard
05/02/2008WO2008052225A2 Mapped nodes in a wire network providing power/communication & load identification
05/02/2008WO2008052130A1 Memory device with configurable delay tracking
05/02/2008WO2008050045A2 Magnetic device with perpendicular magnetisation and comprising an interaction-compensating intermediate layer
05/02/2008WO2008016421A3 Mixed-use memory array with different data states and method for use therewith
05/02/2008WO2007143458A3 Method and apparatus for a dummy sram cell
05/01/2008US20080104312 States encoding in multi-bit flash cells for optimizing error rate
05/01/2008US20080101526 Phase Controlled High Speed Interfaces
05/01/2008US20080101128 Nonvolatile memory device and method of reading information from the same
05/01/2008US20080101127 Reading and writing method for non-volatile memory with multiple data states
05/01/2008US20080101126 Faster programming of highest multi-level state for non-volatile memory
05/01/2008US20080101123 Nand flash memory cell programming
05/01/2008US20080101115 Semiconductor memory device comprising floating body memory cells and related methods of operation
05/01/2008US20080101114 Floating body semiconductor memory device and method of operating the same
05/01/2008US20080101113 Memory device and method of manufacturing the same
05/01/2008US20080101112 Phase change memory device with reduced unit cell size and improved transistor current flow and method for manufacturing the same
05/01/2008US20080101111 Phase change memory device with ensured sensing margin and method of manufacturing the same
05/01/2008US20080101110 Combined read/write circuit for memory
05/01/2008US20080101109 Phase Change Memory, Phase Change Memory Assembly, Phase Change Memory Cell, 2D Phase Change Memory Cell Array, 3D Phase Change Memory Cell Array and Electronic Component
05/01/2008US20080101108 Semiconductor device including storage device and method for driving the same
05/01/2008US20080101107 Ferroelectric semiconductor memory device and method for reading the same
05/01/2008US20080100971 Biosensor and sensing cell array using the same
05/01/2008US20080099854 Semiconductor integrated circuit device and process for manufacturing the same
04/2008
04/30/2008EP1915759A1 Low power multiple bit sense amplifier
04/30/2008EP1497733A4 Destructive-read random access memory system buffered with destructive-read memory cache
04/30/2008DE102007050864A1 Command and address signals communicating device for computer system, has command bus interface with command connecting pins to receive command input signals, and interconnected connector pins to receive address and command input signals
04/30/2008DE102006051591B3 Memory chip i.e. dynamic RAM memory chip, testing method, involves determining that all data outputs of memory chips lie close to logical zero and one, if signal level at input falls below and exceeds threshold level, respectively
04/30/2008DE10120418B4 Gemeinsames Modul für einen DDR-SDRAM und einen SDRAM Common module for a DDR SDRAM and SDRAM
04/30/2008DE10106775B9 Spannungsdetektionsschaltung für ein Halbleiterspeicherbauelement Voltage detection circuit for a semiconductor memory device
04/30/2008CN101170160A Method for manufacturing a resistor random access memory with a self-aligned air gap insulator
04/30/2008CN101170122A Non-volatile multi-bit memory device, its manufacture method and operation method
04/30/2008CN101170121A Bistable programmable resistance type random access memory
04/30/2008CN101170120A Phase change memory cells with dual access devices
04/30/2008CN101170077A Method for manufacturing a resistor random access memory with reduced active area and reduced contact areas
04/30/2008CN101169970A Methods of operating a bistable resistance random access memory
04/30/2008CN101169969A Signal amplifier of deep submicron dynamic memory
04/30/2008CN101169968A Semiconductor storage device
04/30/2008CN101169967A Low power dynamic random access memory and its driving method
04/30/2008CN101169966A Semiconductor memory device
04/30/2008CN101169965A Combined read/write circuit for memory
04/30/2008CN100385572C Semiconductor device and semiconductor storage device
04/30/2008CN100385571C Reference voltage generating method, logic judgement mode and device of ferroelectric capacitor
04/30/2008CN100385570C High speed memory system, memory device, calibration method and method of synchronizing read timing
04/30/2008CN100385569C Memory sense amplifier for memory device
04/30/2008CN100385568C Memory element, method of repairing its defect memory unit automatically and method of its access
04/30/2008CN100385543C Planer electron emitting device unit with improved emitting area and its making process
04/29/2008US7366965 Semiconductor integrated circuit
04/29/2008US7366828 Memory controller, semiconductor integrated circuit device, semiconductor device, microcomputer, and electronic device
04/29/2008US7366827 Method and apparatus for selectively transmitting command signal and address signal
04/29/2008US7366822 Semiconductor memory device capable of reading and writing data at the same time
04/29/2008US7366820 Second-cache driving/controlling circuit, second cache, RAM, and second-cache driving/controlling method
04/29/2008US7366044 Systems and methods for data transfers between memory cells
04/29/2008US7366030 Simultaneous read circuit for multiple memory cells
04/29/2008US7366029 High-performance flash memory data transfer
04/29/2008US7366028 Method of high-performance flash memory data transfer
04/29/2008US7366027 Method and apparatus for erasing memory
04/29/2008US7366024 Method and apparatus for operating a string of charge trapping memory cells
04/29/2008US7366023 Flash memory device
04/29/2008US7366022 Apparatus for programming of multi-state non-volatile memory using smart verify
04/29/2008US7366021 Method and apparatus for sensing flash memory using delta sigma modulation
04/29/2008US7366020 Flash memory device capable of preventing an overerase of flash memory cells and erase method thereof
04/29/2008US7366019 Nonvolatile memory
04/29/2008US7366017 Method for modifying data more than once in a multi-level cell memory location within a memory array
04/29/2008US7366015 Semiconductor integrated circuit device, production and operation method thereof
04/29/2008US7366012 Synchronous memory device with reduced power consumption
04/29/2008US7366011 Power consumption minimization in magnetic random access memory by using the effect of hole-mediated ferromagnetism
04/29/2008US7366010 Magnetic memory
04/29/2008US7366009 Separate write and read access architecture for a magnetic tunnel junction
04/29/2008US7366008 Radiation tolerant SRAM bit
04/29/2008US7366007 Semiconductor memory device
04/29/2008US7366006 SRAM with read assist
04/29/2008US7366005 Ferroelectric memory device and display-driving IC
04/29/2008US7366004 Memory
04/29/2008US7366003 Method of operating a complementary bit resistance memory sensor and method of operation
04/29/2008US7366001 Content addressable memory including main-match lines and sub-match lines
04/29/2008US7365591 Voltage generating circuit
04/29/2008US7365554 Integrated circuit for determining a voltage
04/29/2008US7365398 Compact SRAMs and other multiple transistor structures
04/29/2008US7365373 Thyristor-type memory device
04/29/2008US7365354 Programmable resistance memory element and method for making same
04/29/2008US7364644 Silver selenide film stoichiometry and morphology control in sputter deposition
04/29/2008US7364271 Nozzle arrangement with inlet covering cantilevered actuator