Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
11/2008
11/05/2008CN100431042C Semiconductor device and data writing method therefor
11/05/2008CN100431041C Film magnetic storage of storage unit containing tunnel magnetoresistive element
11/05/2008CN100431039C Reading circuit for reading a memory cell
11/05/2008CN100431038C Control time pulse generator and control time pulse generation method for high-speed sensing amplifier
11/04/2008US7447974 Memory controller method and system compensating for memory cell data losses
11/04/2008US7447973 Memory controller method and system compensating for memory cell data losses
11/04/2008US7447950 Memory device and memory error correction method
11/04/2008US7447805 Buffer chip and method for controlling one or more memory arrangements
11/04/2008US7447101 PG-gated data retention technique for reducing leakage in memory cells
11/04/2008US7447093 Method for controlling voltage in non-volatile memory systems
11/04/2008US7447091 Sense amplifier for semiconductor memory device
11/04/2008US7447087 Semiconductor memory device having memory block configuration
11/04/2008US7447078 Method for non-volatile memory with background data latch caching during read operations
11/04/2008US7447077 Referencing scheme for trap memory
11/04/2008US7447076 Systems for reverse reading in non-volatile memory with compensation for coupling
11/04/2008US7447075 Charge packet metering for coarse/fine programming of non-volatile memory
11/04/2008US7447074 Read-only memory
11/04/2008US7447072 Storage device employing a flash memory
11/04/2008US7447071 Low voltage column decoder sharing a memory array p-well
11/04/2008US7447069 Flash EEprom system
11/04/2008US7447067 Method and apparatus for programming multi level cell flash memory device
11/04/2008US7447066 Memory with retargetable memory cell redundancy
11/04/2008US7447065 Reducing read disturb for non-volatile storage
11/04/2008US7447064 System and method for providing a CMOS compatible single poly EEPROM with an NMOS program transistor
11/04/2008US7447063 Nonvolatile semiconductor memory device
11/04/2008US7447062 Method and structure for increasing effective transistor width in memory arrays with dual bitlines
11/04/2008US7447061 Magnetoresistive memory array circuit
11/04/2008US7447060 MRAM Memory conditioning
11/04/2008US7447059 Semiconductor integrated circuit
11/04/2008US7447058 Write margin of SRAM cells improved by controlling power supply voltages to the inverters via corresponding bit lines
11/04/2008US7447057 Semiconductor integrated circuit device with a plurality of memory cells storing data
11/04/2008US7447056 Method for using a multi-use memory cell and memory array
11/04/2008US7447055 Multiplexer interface to a nanoscale-crossbar
11/04/2008US7445980 Method and apparatus for improving stability of a 6T CMOS SRAM cell
10/2008
10/30/2008WO2008129534A1 Adaptive dynamic reading of flash memories
10/30/2008WO2008129533A1 Adaptive dynamic reading of flash memories
10/30/2008WO2008099348A3 Semiconductor device identifier generation
10/30/2008US20080266989 Sram circuitry
10/30/2008US20080266988 Multi- port memory device for buffering between hosts and non-volatile memory devices
10/30/2008US20080266981 Nonvolatile memory devices and methods of forming the same
10/30/2008US20080266980 Methods for conducting double-side-biasing operations of nand memory arrays
10/30/2008US20080266979 Methods of biasing a multi-level-cell memory
10/30/2008US20080266978 Arrangements for operating a memory circuit
10/30/2008US20080266977 Method for high speed programming of a charge trapping memory with an enhanced charge trapping site
10/30/2008US20080266974 Non-volatile memory having a static verify-read output data path
10/30/2008US20080266973 Reducing power consumption during read operations in non-volatile storage
10/30/2008US20080266970 Programming and/or erasing a memory device in response to its program and/or erase history
10/30/2008US20080266966 Operation method of non-volatile memory and method of improving coupling interference from nitride-based memory
10/30/2008US20080266965 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells
10/30/2008US20080266964 Non-volatile storage with compensation for source voltage drop
10/30/2008US20080266963 Compensating source voltage drop in non-volatile storage
10/30/2008US20080266960 Non-volatile memory and manufacturing method and operating method thereof and circuit system including the non-volatile memory
10/30/2008US20080266955 Sram cell controlled by flash memory cell
10/30/2008US20080266949 Integrated circuits with substrate protrusions, including (but not limited to) floating gate memories
10/30/2008US20080266945 Adaptive detection of threshold levels in memory
10/30/2008US20080266944 Non-volatile memory cell with a hybrid access transistor
10/30/2008US20080266943 Spin-torque MRAM: spin-RAM, array
10/30/2008US20080266942 Multiple level cell phase-change memory device having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices
10/30/2008US20080266941 8/9 and 8/10-bit encoding to reduce peak surge currents when writing phase-change memory
10/30/2008US20080266940 Air Cell Thermal Isolation for a Memory Array Formed of a Programmable Resistive Material
10/30/2008US20080266939 Magnetic memory device
10/30/2008US20080266938 Magnetoresistive device and method of packaging same
10/30/2008US20080266937 Semiconductor device
10/30/2008US20080266936 Memory device using SRAM circuit
10/30/2008US20080266935 Dram storage capacitor without a fixed voltage reference
10/30/2008US20080266934 Nonvolatile memory device and method to control the same
10/30/2008US20080266933 Method and Apparatus for Refreshing Programmable Resistive Memory
10/30/2008US20080266932 Circuit for programming a memory element
10/30/2008US20080266931 Resistive memory device having enhanced resist ratio and method of manufacturing same
10/30/2008US20080266930 Piezoelectrically actuated ultrananocrystalline diamond tip array integrated with ferroelectric or phase change media for high-density memory
10/30/2008US20080266929 Reference cell layout with enhanced rtn immunity
10/30/2008US20080266928 Semiconductor memory device
10/30/2008US20080265285 Microelectronic programmable device and methods of forming and programming the same
10/30/2008US20080265284 Semiconductor device
10/30/2008DE10318607B4 Verbesserte Speicherungszustände in einem Speicher Improved storage conditions in a memory
10/30/2008DE102007016631A1 Storage capacitor for use in e.g. memory cell of dynamic RAM, has conductive material which is provided at distance from capacitor electrode by capacitor dielectric and is extended over lower part of outer side of electrode
10/29/2008EP1986233A2 On-chip reconfigurable memory
10/29/2008EP1986196A1 A spin-torque MRAM: spin-RAM, array
10/29/2008EP1984923A2 Flash memory with coding and signal processing
10/29/2008EP1579483A4 System and method for expanding a pulse width
10/29/2008EP1362339B1 Low-power organic light emitting diode pixel circuit
10/29/2008CN101297372A Method and apparatus for programming/erasing a non-volatile memory
10/29/2008CN101297371A Current driven switched magnetic storage cells having improved read and write margins and magnetic memories using such cells
10/29/2008CN101295763A Resistive memory device and stack structure of resistive random access memory device
10/29/2008CN101295729A Integrated circuit including spacer material layer
10/29/2008CN101295539A Method and apparatus for refreshing programmable resistive memory
10/29/2008CN101295538A Semiconductor device
10/29/2008CN101295537A Reading operation control method of memory body
10/29/2008CN101295536A Booster circuit and memory structure using the same
10/29/2008CN100429724C Semiconductor memory circuit and method for operating the same in a standby mode
10/29/2008CN100429723C Semiconductor memory
10/29/2008CN100429722C Enhanced refresh circuit and method for reduction of dram refresh cycles
10/29/2008CN100429721C Magnetic DASD based on vertical current writing and its control method
10/29/2008CN100429702C Method and apparatus for read bitline clamping for gain cell DRAM devices
10/28/2008US7444563 Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
10/28/2008US7444490 Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress
10/28/2008US7443757 Non-volatile memory and method with reduced bit line crosstalk errors
10/28/2008US7443755 Fuse box of semiconductor device
10/28/2008US7443754 Semiconductor memory device
10/28/2008US7443734 Semiconductor memory device with a voltage generating circuit which generates a plurality of voltages using a small number of items of data
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