Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled
Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116)
04/1990
04/10/1990CA1267731A1 Serial digital signal processing circuitry
04/04/1990EP0361886A2 Improved floating point computation unit
04/04/1990EP0360899A1 Queue comprising a plurality of memory elements
04/03/1990US4914675 Apparatus for efficiently packing data in a buffer
04/03/1990US4914622 Array-organized bit map with a barrel shifter
04/03/1990US4914618 Asynchronous serial communications apparatus with variable length stop bit generation capability
03/1990
03/21/1990EP0359551A2 Semicoductor memory circuit
03/21/1990EP0166772B1 Improvements in or relating to computer systems
03/13/1990US4908614 Image data output apparatus
03/13/1990CA1266720A1 Synchronizing system
02/1990
02/27/1990US4905232 Peripheral repeater box
02/27/1990US4905178 Structure for normalizing a floating point number
02/27/1990US4905175 Digit-serial shifters constructed from basic cells
02/20/1990CA1266130A1 Circular first-in, first-out buffer
02/14/1990EP0354534A2 Semiconductor logic circuit
02/13/1990US4901286 Digital FIFO memory
02/13/1990US4901277 Network data flow control technique
02/13/1990US4901263 Versatile data shifter with sticky bit generation capability
02/07/1990EP0354073A1 Random access memory management system
02/07/1990EP0353942A2 A ripple-through FIFO memory
02/07/1990EP0353826A1 Statistical-coding device producing code words having a variable number of binary elements
02/06/1990US4899352 System and device to interface asynchronous apparatuses
02/06/1990US4899304 Overflow detection circuit
02/06/1990US4899147 Data compression/decompression apparatus with throttle, start-up and backward read controls
01/1990
01/30/1990CA1265271A1 Bit interleaved multiplexer system providing byte synchronization for communicating apparatuses
01/30/1990CA1265254A1 Programmably controlled shifting mechanism in a programmable unit having variable data path widths
01/25/1990WO1990000837A1 Method and apparatus for encoding, decoding and transmitting data in compressed form
01/24/1990EP0203993B1 Queue administration method and apparatus
01/17/1990EP0350966A2 Barrel shifter
01/16/1990US4894797 FIFO data storage system using PLA controlled multiplexer for concurrent reading and writing of registers by different controllers
01/10/1990EP0350281A1 Method and apparatus for encoding, decoding and transmitting data in compressed form
01/10/1990CN1038711A Box display device for word processor
01/02/1990US4891788 FIFO with almost full/almost empty flag
12/1989
12/28/1989WO1989012866A1 Intermediate spreadsheet structure
12/26/1989US4890251 Arithmetic shifter with sign extend facility
12/26/1989US4890226 Memory access control apparatus having empty real address storing memory and logical address/reat address pair storing memory
12/20/1989EP0347032A2 Record format emulation
12/19/1989US4888741 Memory with cache register interface structure
12/19/1989US4888739 First-in first-out buffer memory with improved status flags
12/19/1989US4888727 Peripheral controller with paged data buffer management
12/14/1989WO1989012363A2 Data compression/decompression apparatus
12/13/1989EP0345807A2 Line memory for speed conversion
12/13/1989EP0345608A2 Data compression system and method with buffer control
12/12/1989US4887232 Apparatus and method for performing a shift operation in a multiplier array circuit
12/05/1989USH718 Multi-sensor buffer interface
11/1989
11/29/1989EP0344052A1 Modular memory
11/29/1989EP0343668A2 Normalization control system for floating point arithmetic operations
11/21/1989US4882754 Data compression system and method with buffer control
11/21/1989US4882710 FIFO memory including dynamic memory elements
11/21/1989CA1263195A1 Fifo memory with decreased fall-through delay
11/15/1989EP0342107A2 Flag for a FIFO
11/15/1989EP0341887A2 Frame buffer memory device
11/14/1989US4881167 Data memory system
11/14/1989US4881163 Computer system architecture employing cache data line move-out queue buffer
11/02/1989DE3910803A1 High-speed output buffer
10/1989
10/31/1989US4878197 Data communication apparatus
10/25/1989EP0338794A2 Apparatus for marking a recorded signal
10/18/1989EP0337471A2 Serial input-output circuit for forward and backward producing bits from bidirectional shift registers
10/17/1989US4875224 Asynchronous communication systems
10/17/1989US4875196 Method of operating data buffer apparatus
10/17/1989US4875180 Multi-function scaler for normalization of numbers
10/10/1989US4873703 Synchronizing system
10/10/1989US4873667 FIFO buffer controller
10/10/1989US4873666 Message FIFO buffer controller
10/10/1989US4873665 Dual storage cell memory including data transfer circuits
10/05/1989WO1989009441A1 Apparatus and method for floating point normalization prediction
10/05/1989WO1989009439A1 Four phase shifter
10/04/1989EP0335462A1 Data processing system with cyclic data buffering, selecting means for selecting memory addresses, suitable for use in such a system
10/03/1989US4872132 Method and means for block floating point arithmetic
10/03/1989US4872128 High speed data processing unit using a shift operation
10/03/1989US4872009 Method and apparatus for data compression and restoration
09/1989
09/26/1989US4870415 Data compression system with expansion protection
09/26/1989CA1260559A1 Mask signal generator
09/20/1989EP0332972A1 Method and means for data transfer
09/19/1989US4868737 Method and arrangement in which capacity of a related storage medium is checked when buffering data
09/12/1989US4866440 Method for compressing and restoring data series and apparatus for realizing same
09/06/1989EP0331487A2 Data transfer control system
09/06/1989CN1035382A Message fifo buffer controller
09/06/1989CN1035381A Fifo buffer controller
09/06/1989CN1035245A Microcomputerized controller of respirator
09/05/1989US4864543 First-in, first-out memory with counter address pointers for generating multiple memory status flags
09/05/1989US4864495 Apparatus for controlling vacant areas in buffer memory in a pocket transmission system
08/1989
08/30/1989EP0329776A1 Method and apparatus for interconnecting busses in a multibus computer system
08/30/1989EP0329692A1 Data buffer/switch
08/29/1989US4862419 High speed pointer based first-in-first-out memory
08/29/1989US4862167 Adaptive data compression method and apparatus
08/22/1989US4860293 Supervision circuit for a non-encoded binary bit stream
08/22/1989US4860202 IR decoder system
08/22/1989US4860193 System for efficiently transferring data between a high speed channel and a low speed I/O device
08/22/1989CA1258714A1 Maintaining i/o compatibility with differing computer types
08/16/1989CN1034821A Digital fifo memory
08/15/1989US4858114 Emulation system for automatically modifying I/O translation tables in programs designed to run on different types of computer
08/10/1989WO1989007372A1 Apparatus for efficiently packing data in a buffer
08/09/1989EP0327115A1 Serial access memory system provided with improved cascade buffer circuit
08/09/1989EP0326560A1 Arrangement for data compression
08/02/1989EP0326136A2 Queue device capable of quickly transferring a digital signal unit of a word length different from a single word length
08/02/1989EP0326006A2 Format converting circuit for numeric data
07/1989
07/26/1989EP0325423A2 An error detecting circuit for a decoder
07/25/1989US4852127 Universal protocol data receiver
07/19/1989EP0324374A2 Transistor matrix shifter
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