| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 07/26/2005 | US6922090 Transition signaling circuit and arbitrator using this circuit |
| 07/26/2005 | US6922088 Self-determining electronic control circuit |
| 07/26/2005 | US6922085 Comparator and method for detecting a signal using a reference derived from a differential data signal pair |
| 07/26/2005 | US6922083 High speed sampling receiver with reduced output impedance |
| 07/26/2005 | US6922079 Output driver apparatus and method thereof |
| 07/26/2005 | US6922078 Programmable logic device with enhanced wide and deep logic capability |
| 07/26/2005 | US6922077 Hybrid compensated buffer design |
| 07/26/2005 | US6922074 ASIC architecture for active-compensation of a programmable impedance I/O |
| 07/26/2005 | US6922073 Circuit configuration for signal balancing in antiphase bus drivers |
| 07/26/2005 | US6922071 Setting multiple chip parameters using one IC terminal |
| 07/26/2005 | US6921950 Semiconductor device |
| 07/21/2005 | WO2005067147A1 Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array |
| 07/21/2005 | WO2005066832A2 Integrated circuit with cascading dsp slices |
| 07/21/2005 | WO2005066821A2 Using feedback to select transmitting voltage |
| 07/21/2005 | WO2003083872A3 Low-power high-performance memory cell and related methods |
| 07/21/2005 | US20050160200 Processor system, DMA control circuit, DMA control method, control method for DMA controller, graphic processing method, and graphic processing circuit |
| 07/21/2005 | US20050157781 Signal receiver with data precessing function |
| 07/21/2005 | US20050157780 Signaling system with selectively-inhibited adaptive equalization |
| 07/21/2005 | US20050156844 Semiconductor circuit |
| 07/21/2005 | US20050156653 Switchable power domains for 1.2v and 3.3v pad voltages |
| 07/21/2005 | US20050156651 RS-232 transmitter apparatus |
| 07/21/2005 | US20050156644 Power converter circuitry and method |
| 07/21/2005 | US20050156642 Feed-forward circuit for reducing delay through an input buffer |
| 07/21/2005 | US20050156636 Output circuit |
| 07/21/2005 | US20050156633 Circuits and methods for high-capacity asynchronous pipeline processing |
| 07/21/2005 | US20050156632 Micropipeline stage controller and control scheme |
| 07/21/2005 | US20050156630 Signal level conversion circuit |
| 07/21/2005 | US20050156629 High current 5v tolerant buffer using a 2.5 volt power supply |
| 07/21/2005 | US20050156628 Moderate current 5V tolerant buffer using a 2.5 volt power supply |
| 07/21/2005 | US20050156627 Programmable array logic circuit employing non-volatile ferromagnetic memory cells |
| 07/21/2005 | US20050156626 Optimal mapping of LUT based FPGA |
| 07/21/2005 | US20050156624 Receiver circuit arrangement having an inverter circuit |
| 07/21/2005 | US20050156623 Method and apparatus for implementing power control in multi-voltage i/o circuits |
| 07/21/2005 | US20050156621 Transceiver providing high speed transmission signal using shared resources and reduced area |
| 07/21/2005 | US20050156620 Radiation hardening of logic circuitry using a cross enabled, interlocked logic system and method |
| 07/21/2005 | US20050156305 Semiconductor integrated circuit device |
| 07/21/2005 | DE4336720B4 Eingabepuffer Input buffer |
| 07/21/2005 | DE102004060571A1 Slew rate adjusting apparatus for e.g. synchronous dynamic RAM, has slew rate control signal generation block to output slew rate control signals, and data output buffer adjusting slew rate of data signal input by control signals |
| 07/21/2005 | DE102004057273A1 Spannungserzeugungsschaltung Voltage generating circuit |
| 07/21/2005 | DE102004045231A1 Halbleitervorrichtung, die eine Fehlfunktion verhindern kann, welche von einem in einer Pegelschiebeschaltung erzeugten falschen Signal verursacht ist A semiconductor device which can prevent a malfunction which is caused by a signal generated in a level shift circuit wrong signal |
| 07/21/2005 | DE102004038666A1 Ausgangspufferanstiegsgeschwindigkeitssteuerung unter Verwendung eines Taktsignals Output buffer slew rate control using a clock signal |
| 07/21/2005 | DE102004036782A1 Busagent, der mehrere Referenzpegel aufweist Bus agent having a plurality of reference level |
| 07/21/2005 | CA2548327A1 Integrated circuit with cascading dsp slices |
| 07/20/2005 | EP1554805A2 Programmable logic device |
| 07/20/2005 | EP1554743A1 Method and apparatus for bootstrapping a programmable antifuse circuit |
| 07/20/2005 | EP1410053B1 Integrated testing of serializer/deserializer in fpga |
| 07/20/2005 | EP1177630B1 Apparatus and methods for dynamically defining variably sized autonomous sub-arrays within a programmable gate array |
| 07/20/2005 | CN1643793A Implementation of wide multiplexers in reconfigurable logic |
| 07/20/2005 | CN1643792A Configuration memory implementation for lut-based reconfigurable logic architectures |
| 07/20/2005 | CN1643680A Adaptive threshold voltage control with positive body bias for N and P-channel transistors |
| 07/20/2005 | CN1642009A Voltage transfer circuit |
| 07/20/2005 | CN1642005A Oscillator circuit operating with a variable driving voltage |
| 07/20/2005 | CN1641877A IC, RAM on IC and method of holding perfomance in IC |
| 07/20/2005 | CN1641651A Method for implementing physical design for dynamically reconfigurable logic circuit |
| 07/20/2005 | CN1641650A Logical assembly capable of configuration without local configuration storage but having parallel configuration storage |
| 07/20/2005 | CN1641614A Processor system, DMA control circuit, DMA control method, control method for DMA controller, graphic processing method, and graphic processing circuit |
| 07/19/2005 | US6920627 Reconfiguration of a programmable logic device using internal control |
| 07/19/2005 | US6920626 Method for re-encoding a decoder |
| 07/19/2005 | US6920594 Scan flip-flop circuit, logic macro, scan test circuit, and method for laying out the same |
| 07/19/2005 | US6920577 Clock selection circuit for selecting between an external clock and a clock generated by comparing a count value with a setting value |
| 07/19/2005 | US6920570 Level shifter control circuit with delayed switchover to low-power level shifter |
| 07/19/2005 | US6920316 High performance integrated circuit regulator with substrate transient suppression |
| 07/19/2005 | US6920187 Constant delay zero standby differential logic receiver and method |
| 07/19/2005 | US6920071 Semiconductor integrated circuit device |
| 07/19/2005 | US6919873 Liquid crystal display apparatus having level conversion circuit |
| 07/19/2005 | US6919754 Fuse detection circuit |
| 07/19/2005 | US6919752 Level shifter and latch with the same built in |
| 07/19/2005 | US6919743 Drive circuit with low current consumption |
| 07/19/2005 | US6919739 Feedforward limited switch dynamic logic circuit |
| 07/19/2005 | US6919738 Output buffer circuit, memory chip, and semiconductor device having a circuit for controlling buffer size |
| 07/19/2005 | US6919737 Voltage-level converter |
| 07/19/2005 | US6919736 Field programmable gate array having embedded memory with configurable depth and width |
| 07/19/2005 | US6919735 Skewed nor and nand rising logic devices for rapidly propagating a rising edge of an output signal |
| 07/19/2005 | US6919647 SRAM cell |
| 07/19/2005 | US6919603 Efficient protection structure for reverse pin-to-pin electrostatic discharge |
| 07/14/2005 | WO2005064796A1 Load-aware circuit arrangement |
| 07/14/2005 | WO2005064791A1 Variable attenuator |
| 07/14/2005 | WO2005064783A2 Tuneable spin torque device for generating an oscillating signal and method for tuning |
| 07/14/2005 | WO2005064590A1 Method for ultra-fast controlling of a magnetic cell and related devices |
| 07/14/2005 | WO2005064456A1 Programmable logic circuit control apparatus, programmable logic circuit control method and program |
| 07/14/2005 | US20050152198 Logical operation circuit and logical operation method |
| 07/14/2005 | US20050151579 Semiconductor integrated circuit |
| 07/14/2005 | US20050151574 High voltage output level shifter |
| 07/14/2005 | US20050151570 Integrated circuit having reduced substate bounce |
| 07/14/2005 | US20050151568 Gate driver with level shift between static wells with no power supply |
| 07/14/2005 | US20050151565 Digital signal buffer circuit |
| 07/14/2005 | US20050151564 I/O cell configuration for multiple I/O standards |
| 07/14/2005 | US20050151561 Output driver for use in semiconductor device |
| 07/14/2005 | US20050151560 Scan flip flop, semiconductor device, and production method of semiconductor device |
| 07/13/2005 | CN1639690A 半导体装置 Semiconductor device |
| 07/13/2005 | CN1638281A Semiconductor circuit |
| 07/13/2005 | CN1638280A Gate driver with level shift between static wells with no power supply |
| 07/13/2005 | CN1638279A 接收装置 Receiver |
| 07/13/2005 | CN1638276A Delay circuit and display including the same |
| 07/13/2005 | CN1638127A 半导体集成电路器件 The semiconductor integrated circuit device |
| 07/13/2005 | CN1638113A Semiconductor integrated circuit apparatus |
| 07/13/2005 | CN1637748A Reconfigurable circuit, processor having reconfigurable circuit |
| 07/13/2005 | CN1637737A In-circuit configuration architecture with configuration on initialization function |
| 07/13/2005 | CN1637736A In-circuit configuration architecture with non-volatile configuration store |
| 07/13/2005 | CN1637671A 现场可编程门阵列 Field Programmable Gate Arrays |