Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
06/2005
06/02/2005DE10323012B4 Programmierbare, integrierte Schaltungsanordnung und Verfahren zur Programmierung einer integrierten Schaltungsanordnung Programmable, integrated circuit and method for programming an integrated circuit device
06/02/2005DE102004050464A1 Semiconductor output circuit for use with motor vehicle electric equipment, has NMOS which discharges electric charge of gate of source follower at lower rate than another NMOS when output voltage is lower than power supply voltage
06/01/2005EP1536346A2 Reconfigurable logic for a computer
06/01/2005EP1536345A2 Programmable configuration integrated circuit
06/01/2005EP1536332A2 Programmable configuration integrated circuit
06/01/2005EP1536124A1 Drive device for electrical injectors of an internal combustion engine common rail fuel injection system
06/01/2005EP1535394A2 Loosely-biased heterogeneous reconfigurable arrays
06/01/2005EP1535393A2 Circuits with improved power supply rejection
06/01/2005EP1535308A2 Protected dual-voltage microcircuit power arrangement
06/01/2005CN1623239A Light-emitting device having PNPN structure and light-emitting device array
06/01/2005CN1622463A 电平移位电路 Level shift circuit
06/01/2005CN1622462A 半导体器件 Semiconductor devices
06/01/2005CN1622220A Input buffer for detecting an input signal
06/01/2005CN1204688C Input/output circuit capable of allowing variable voltage
06/01/2005CN1204677C Grid circuit for driving insulated gate bipolar transistor inverter
06/01/2005CN1204506C Storing device
05/2005
05/31/2005US6901526 Digital bus synchronizer for generating read reset signal
05/31/2005US6900691 Semiconductor integrated circuit
05/31/2005US6900690 Low-power high-performance integrated circuit and related methods
05/31/2005US6900681 Phase interpolator and receiver for adjusting clock phases into data phases
05/31/2005US6900670 Current-controlled CMOS logic family
05/31/2005US6900667 Logic constructions and electronic devices
05/31/2005US6900666 Dual threshold voltage and low swing domino logic circuits
05/31/2005US6900663 Low voltage differential signal driver circuit and method
05/31/2005US6900659 Methods and apparatus for loading data into a plurality of programmable devices
05/31/2005US6900658 Null convention threshold gate
05/31/2005US6900628 Semiconductor integrated circuit allowing proper detection of pin contact failure
05/31/2005US6900478 Multi-threshold MIS integrated circuit device and circuit design method thereof
05/26/2005WO2005048547A1 Tx line driver with common mode idle state and selectable slew rates
05/26/2005US20050114814 Multiple voltage integrated circuit and design method therefor
05/26/2005US20050114803 Low power buffer implementation
05/26/2005US20050114424 Multibit bit adder
05/26/2005US20050111604 Serial data communication system having plurality of data transmission paths
05/26/2005US20050111265 Semiconductor device using SCL circuit
05/26/2005US20050110560 Apparatus and method for stabilizing a boosted voltage, apparatus and method for generating a boosted voltage having the same
05/26/2005US20050110557 Power efficiency control output buffer
05/26/2005US20050110556 Bootstrap driver
05/26/2005US20050110553 Level shifter
05/26/2005US20050110546 Method and integrated circuit apparatus for reducing simultaneously switching output
05/26/2005US20050110543 Digital signal transmission circuit and method of designing it
05/26/2005US20050110531 Driver circuit
05/26/2005US20050110530 Differential output circuit
05/26/2005US20050110525 Current-mode logic circuit
05/26/2005US20050110524 Synchronizing signals between clock domains
05/26/2005US20050110523 Noisy clock test method and apparatus
05/26/2005US20050110522 Multistage dynamic domino circuit with internally generated delay reset clock
05/26/2005US20050110521 Dual mode analog differential and cmos logic circuit
05/26/2005US20050110520 Input stage for mixed-voltage-tolerant buffer without leakage issue
05/26/2005US20050110519 Single supply level converter
05/26/2005US20050110518 Logic circuit apparatus and timeshare operating method of a programmable logic circuit
05/26/2005US20050110517 Hybrid compensated buffer design
05/26/2005US20050110516 Semiconductor device
05/25/2005EP1533904A1 Integrated circuit technology
05/25/2005EP1533901A2 CMOS circuits with protection for a single event upset
05/25/2005EP1314250B1 Protection for input buffers of flash memories
05/25/2005EP1063529B1 Method and apparatus for testing field programmable gate arrays
05/25/2005CN1619965A Differential output circuit
05/25/2005CN1619964A Semiconductor integrated circuit, logic operation circuit, and flip flop
05/25/2005CN1203614C Fast discrete fourier transform and inverse transform integrated circuit using prime factor algorithm
05/25/2005CN1203600C New-type digital quantity output circuit
05/25/2005CN1203434C Method and system for programming of FPGA on PC card without additional hardware
05/24/2005US6898778 Semiconductor integrated circuit and method of manufacturing the same
05/24/2005US6898777 Block level routing architecture in a field programmable gate array
05/24/2005US6898724 System for latching an output signal generated by comparing complimentary strobe signals and a data signal in response to a comparison of the complimentary strobe signals
05/24/2005US6898719 Microcomputer comprising electric power source without condenser for backup for changing power source level based on power supply stopped or resumed
05/24/2005US6898097 Floating-gate analog circuit
05/24/2005US6897714 Reference voltage generating circuit
05/24/2005US6897697 Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process
05/24/2005US6897695 Semiconductor integrated circuit device and method of detecting delay error in the same
05/24/2005US6897688 Input/output buffer having analog and digital input modes
05/24/2005US6897685 Differential data transmitter
05/24/2005US6897684 Input buffer circuit and semiconductor memory device
05/24/2005US6897680 Interconnection resources for programmable logic integrated circuit devices
05/24/2005US6897679 Programmable logic array integrated circuits
05/24/2005US6897676 Configuration enable bits for PLD configurable blocks
05/24/2005US6897643 Integrated circuit driver having stable bootstrap power supply
05/24/2005US6897497 Methods, apparatus, and systems for reducing interference on nearby conductors
05/19/2005WO2004073293A3 40-gb/s clock and data recovery circuit in 0.18 micrometers technology
05/19/2005US20050108290 Logic computing system and method
05/19/2005US20050105507 Power savings in serial link transmitters
05/19/2005US20050104653 Multiple circuit blocks with interblock control and power conservation
05/19/2005US20050104649 Semiconductor device
05/19/2005US20050104647 Level shifter circuit and method for controlling voltage levels of clock signal and inverted clock signal for driving gate lines of amorphous silicon gate-thin film transistor liquid crystal display
05/19/2005US20050104645 Circuit for generating from low voltage edges higher voltage pulses having precise amplitudes and durations
05/19/2005US20050104625 Data input/output buffer and semiconductor memory device using the same
05/19/2005US20050104623 Method and apparatus for receiver detection on a PCI-Express bus
05/19/2005US20050104622 Output buffer with low-voltage devices to driver high-voltage signals for PCI-X applications
05/19/2005US20050104621 Device and data processing method employing the device
05/19/2005US20050104620 Semiconductor device
05/19/2005US20050104619 Method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time
05/19/2005US20050104618 Low rise/fall skewed input buffer compensating process variation
05/19/2005US20050104133 Semiconductor integrated circuit device
05/19/2005DE10344872A1 Integrierte Schaltung mit Schutz vor elektrostatischer Entladung Integrated circuit with protection against electrostatic discharge
05/19/2005DE102004045527A1 Configurable logic device for data signal processing using dynamic configuration of multiplexer via configuration signals provided for multiplexer control inputs by external control signal sources
05/18/2005CN1617449A Method for producing ternary signal and circuit device
05/18/2005CN1617448A Dynamic logic return-to-zero latching mechanism, latching method and dynamic latching circuit
05/18/2005CN1617446A Frequency multiplication system based on full digital logic circuit
05/18/2005CN1617336A 半导体集成电路装置 The semiconductor integrated circuit device
05/18/2005CN1617260A Encoding circuit for semiconductor device and redundancy control circuit using the same
05/18/2005CN1617120A Signal transmission system, and signal transmission line
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