Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
06/2005
06/28/2005US6911846 Method and apparatus for a 1 of N signal
06/28/2005US6911843 Data transfer device for transferring data between blocks of different clock domains
06/28/2005US6911842 Low jitter clock for a physical media access sublayer on a field programmable gate array
06/28/2005US6911841 Programmable logic device with high speed serial interface circuitry
06/28/2005US6911840 Integrated circuit with overclocked dedicated logic circuitry
06/28/2005US6911703 Semiconductor integrated circuit device operating with low power consumption
06/23/2005WO2005057789A1 Circuit element
06/23/2005WO2005057414A1 Method and apparatus for receiver detection on a pci-express bus
06/23/2005US20050138509 Systems and methods for circuit testing
06/23/2005US20050138502 Test mode circuit of semiconductor device
06/23/2005US20050138445 Logic circuit system and method of changing operating voltage of a programmable logic circuit
06/23/2005US20050138103 Novel adder structure with midcycle latch for power reduction
06/23/2005US20050135813 Linear full-rate phase detector and clock and data recovery circuit
06/23/2005US20050135489 Noise-tolerant signaling schemes supporting simplified timing and data recovery
06/23/2005US20050135424 Synchronous/asynchronous interface circuit and electronic device
06/23/2005US20050135174 Power-up signal generator for semiconductor memory devices
06/23/2005US20050135168 Apparatus for adjusting slew rate in semiconductor memory device and method therefor
06/23/2005US20050135033 Semiconductor integrated circuit apparatus
06/23/2005US20050134435 Semiconductor device and driving method thereof
06/23/2005US20050134358 Method and apparatus switching a semiconductor switch with a multi-state drive circuit
06/23/2005US20050134332 Programmable high speed I/O interface
06/23/2005US20050134331 Input buffer circuit including reference voltage monitoring circuit
06/23/2005US20050134320 Actuation circuit for MEMS structures
06/23/2005US20050134319 Logic circuit
06/23/2005US20050134317 Logic circuit arrangement
06/23/2005US20050134316 Midcycle latch for power saving and switching reduction
06/23/2005US20050134315 Output circuit
06/23/2005US20050134314 Method and circuit for translating a differential signal to complmentary CMOS levels
06/23/2005US20050134313 Input buffer and semiconductor device including the same
06/23/2005US20050134312 Level shifter utilizing input controlled zero threshold blocking transistors
06/23/2005US20050134311 Level shifter
06/23/2005US20050134310 One-level zero-current-state exclusive or (XOR) gate
06/23/2005US20050134309 Macrocell, integrated circuit device, and electronic instrument
06/23/2005US20050134308 Reconfigurable circuit, processor having reconfigurable circuit, method of determining functions of logic circuits in reconfigurable circuit, method of generating circuit, and circuit
06/23/2005US20050134307 Offset cancellation in a multi-level signaling system
06/23/2005US20050134306 High speed signaling system with adaptive transmit pre-emphasis and reflection cancellation
06/23/2005US20050134305 High speed signaling system with adaptive transmit pre-emphasis
06/23/2005US20050134304 Circiut for performing on-die termination operation in semiconductor memory device and its method
06/23/2005US20050134303 Calibration methods and circuits for optimized on-die termination
06/23/2005US20050134246 Voltage generation circuit
06/23/2005DE19983197B4 Verfahren und Einrichtung für ein schnelles Programmieren während der Herstellung und für In-System-Schreiboperationen bei niedriger Spannung für ein programmierbares logisches Bauelement Method and apparatus for a fast programming during manufacturing and for in-system write operations at a low voltage for a programmable logic device
06/23/2005DE19882086B4 Verfahren und Vorrichtung zum Implementieren einer adiabatischen Logikfamilie Method and apparatus for implementing an adiabatic logic family
06/23/2005DE10330825A1 Integrierter Schaltkreis Integrated circuit
06/23/2005DE102004055679A1 Prozessvariationsausgleichender Eingangspuffer mit niedrigem Anstiegs/Abfallversatz Process variation-compensated input buffer with low rise / fall displacement
06/23/2005DE102004052524A1 Voltage converter for use in portable electronic system, has controller connected to drivers for performing transition of input signal to output signal, where one driver is in active state for only predetermined time period
06/22/2005EP1545005A1 Programmable input buffer
06/22/2005EP1545004A1 Semiconductor switch with a multi-state driver
06/22/2005EP1544740A2 Self-reparable semiconductor
06/22/2005EP1543618A1 Transistor circuit
06/22/2005EP1405154B1 Transmitter circuit comprising timing deskewing means
06/22/2005CN1631014A Differential line driver with on-chip termination
06/22/2005CN1630193A Level shifter utilizing input controlled zero threshold blocking transistors
06/22/2005CN1630192A Signal level shift circuit
06/22/2005CN1630191A Input buffer and semiconductor device including the same
06/22/2005CN1630186A Voltage generation circuit
06/22/2005CN1630172A 半导体器件 Semiconductor devices
06/22/2005CN1630082A Self-reparable semiconductor and system thereof
06/22/2005CN1629982A Apparatus for adjusting slew rate in semiconductor memory device and method therefor
06/22/2005CN1629917A Drive chip and display device with the same
06/22/2005CN1629913A Display device having an improved voltage level converter circuit
06/22/2005CN1629883A 半导体器件及其驱动方法 Semiconductor device and method of driving
06/22/2005CN1629762A Current switch circuit, amplifier, and mobile terminal
06/21/2005US6910160 System, method, and computer program product for preserving trace data after partition crash in logically partitioned systems
06/21/2005US6909922 Apparatus, method and computer system for reducing power consumption of a processor or processors upon occurrence of a failure condition affecting the processor or processors
06/21/2005US6909852 Linear full-rate phase detector and clock and data recovery circuit
06/21/2005US6909767 Logic circuit
06/21/2005US6909414 Driver circuit and liquid crystal display device
06/21/2005US6909309 Current-controlled CMOS circuits with inductive broadbanding
06/21/2005US6909308 Increasing drive strength and reducing propagation delays through the use of feedback
06/21/2005US6909307 Bidirectional bus driver and bidirectional bus circuit
06/21/2005US6909306 Programmable multi-standard I/O architecture for FPGAS
06/21/2005US6909305 Digitally controlled impedance driver matching for wide voltage swings at input/output node and having programmable step size
06/21/2005US6909159 Method and apparatus to make a semiconductor chip susceptible to radiation failure
06/21/2005CA2213273C Output characteristics stabilization of cmos devices
06/16/2005WO2005055427A1 Clocked inverter circuit, latch circuit, shift register circuit, circuit for driving display device, and display device
06/16/2005WO2005055184A1 Transistor circuit, pixel circuit, display device, and drive method thereof
06/16/2005WO2005036353A3 Method and apparatus for a chaotic computing module
06/16/2005WO2005031973A3 Cmos circuit system
06/16/2005WO2004021355A3 Electronic device with data storage device
06/16/2005US20050132243 Method and apparatus to minimize power and ground bounce in a logic device
06/16/2005US20050130501 Method and system for reducing aggregate impedance discontinuity between expansion connectors
06/16/2005US20050129167 Gray code counter
06/16/2005US20050128850 Integrated logic circuit and hierarchical design method thereof
06/16/2005US20050128670 Input/output buffer protection circuit
06/16/2005US20050127997 Adjusting methods of arithmetic multiplying circuit, drive circuit, and phase margin
06/16/2005US20050127977 Semiconductor device
06/16/2005US20050127971 Redundant single event upset supression system
06/16/2005US20050127967 Method and apparatus for controlling slew
06/16/2005US20050127959 Frequency divider system
06/16/2005US20050127958 Series terminated CMOS output driver with impedance calibration
06/16/2005US20050127957 I/O circuit using low voltage transistors which can tolerate high voltages even when power supplies are powered off
06/16/2005US20050127956 Output driver for semiconductor device
06/16/2005US20050127955 Low power output driver
06/16/2005US20050127953 5 Volt tolerant IO scheme using low-voltage devices
06/16/2005US20050127952 Non-inverting domino register
06/16/2005US20050127951 Circuit and associated methodology
06/16/2005US20050127950 Feedforward limited switch dynamic logic circuit
06/16/2005US20050127949 Low switching power limited switch dynamic logic
06/16/2005US20050127948 Performance increase technique for use in a register file having dynamically boosted wordlines
06/16/2005US20050127947 Output buffer slew rate control using clock signal
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