Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
11/2005
11/01/2005US6960944 High voltage tolerant differential input receiver
11/01/2005US6960941 Latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits
11/01/2005US6960939 Limited switch dynamic logic circuit with keeper
11/01/2005US6960938 Enhanced CMOS circuit to drive DC motors
11/01/2005US6960937 Power-up and enable control circuits for interconnection arrays in programmable logic devices
11/01/2005US6960936 Configurable electronic device with mixed granularity
11/01/2005US6960935 Method and apparatus for cascade programming a chain of cores in an embedded environment
11/01/2005US6960934 FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
11/01/2005US6960933 Variable data width operation in multi-gigabit transceivers on a programmable logic device
11/01/2005US6960929 Superconductive crossbar switch
11/01/2005US6960915 Electric circuit system
10/2005
10/27/2005WO2005101254A2 High speed transient immune differential level shifting device
10/27/2005WO2004107408A3 Modular array defined by standard cell logic
10/27/2005WO2003010642A3 Method and apparatus for controlling signal states and leakage current during a sleep mode
10/27/2005US20050240891 Method of switching a power supply of voltage domains of a semiconductor circuit, and corresponding semiconductor circuit
10/27/2005US20050239431 Transmission circuit, CMOS semiconductor device, and design method thereof
10/27/2005US20050237792 Magnetic memory device structure
10/27/2005US20050237683 Semiconductor integrated circuit device
10/27/2005US20050237102 Semiconductor integrated circuit device
10/27/2005US20050237100 CMOS-based receiver for communications applications
10/27/2005US20050237099 Level conversion circuit
10/27/2005US20050237095 Frequency output circuit
10/27/2005US20050237094 Impedance controlled output driver
10/27/2005US20050237092 Charge pump circuit reducing noise and charge error and PLL circuit using the same
10/27/2005US20050237085 Output buffer circuit
10/27/2005US20050237084 Voltage translator having minimized power dissipation
10/27/2005US20050237083 Programmable system on a chip
10/27/2005US20050237082 Integrated circuit output driver circuitry with programmable preemphasis
10/27/2005US20050237043 Power circuit
10/27/2005DE202005011873U1 Circuit to convert binary to ternary data based on ternary and quaternary logic has ternary full adder with pn binary or gates
10/27/2005DE202005011872U1 Ternary bus driver for connecting first and second binary coincidence circuits, is based on ternary and quaternary logic and combines ternary OR or AND gates with an inverted OR-OR dual gate
10/27/2005DE202005011871U1 Ternary erase and read memory based on ternary and quaternary logic has pnp or or dual gate address decoder and four logic values
10/27/2005DE202005011870U1 Circuit for ternary signal processing based on ternary and quaternary logic passes ternary signals through gates in logical relation and converts to ternary signal at end stage
10/27/2005DE202005011869U1 Circuit to convert ternary to binary data on basis of ternary and quaternary logic has binary full adder linked to many pnp logic or or dual gates
10/27/2005DE202005011868U1 Master slave flip flop for ternary thrust register based on ternary and quaternary logic has two ternary flip flops connected to inverter and four potential levels and logic numbers
10/27/2005DE202005011867U1 Flip-flop for a ternary counter and divisor based on ternary and quaternary logic links first and second register-storage flip-flops to a ternary wheel gate for detecting a timing signal
10/27/2005DE202005011865U1 Logic data processing circuit based on ternary and quaternary logic, uses four different potential levels that give four logic numbers for arithmetic circuits
10/27/2005DE202005011864U1 Ternary flip flop pre driver based on ternary and quaternary logic has pnp logic or or dual gate and and p binary and gate and carry signal
10/27/2005DE202005011859U1 Half subtractor circuit based on ternary and quaternary logic combines input PNP OR-OR dual gates, with a arithmetically linked binary gates and a final ternary stage
10/27/2005DE202005011849U1 Circuit for a full multiplier based on ternary and quaternary logic has pnp and and and or or dual gates and four logic numbers from four different voltage levels
10/27/2005DE102004016920A1 Verfahren zum Schalten einer Spannungsversorgung von Spannungsdomänen einer Halbleiterschaltung und entsprechende Halbleiterschaltung A method for switching a power supply voltage domains of a semiconductor circuit, and corresponding semiconductor circuit
10/26/2005EP1589661A1 Circuit having a controllable slew rate
10/26/2005EP1589660A2 Frequency output circuit
10/26/2005CN1689231A Fail-safe method and circuit
10/26/2005CN1689230A Voltage generating circuit, voltage generating device and semiconductor device using the same, and driving method thereof
10/26/2005CN1689106A Electronic device with data storage device
10/26/2005CN1225086C 可编程序电压监控电路 Programmable voltage monitoring circuit
10/25/2005US6958930 Magnetoelectronic device with variable magnetic write field
10/25/2005US6958638 Slew rate controlling method and system for output data
10/25/2005US6958632 Symmetric voltage follower buffer
10/25/2005US6958629 Single stage, level restore circuit with mixed signal inputs
10/25/2005US6958628 Three-transistor NAND and NOR gates for two-phase clock generators
10/25/2005US6958627 Asynchronous pipeline with latch controllers
10/25/2005US6958626 Off chip driver
10/25/2005US6958625 Programmable logic device with hardwired microsequencer
10/25/2005US6958621 Method and circuit for element wearout recovery
10/20/2005WO2005098954A1 Via configurable architecture for customization of analog circuitry in a semiconductor device
10/20/2005US20050235173 Reconfigurable integrated circuit
10/20/2005US20050233701 Systems and methods for adjusting an output driver
10/20/2005US20050232297 Implementation of wide multiplexers in reconfigurable logic
10/20/2005US20050232056 Electronic device with data storage device
10/20/2005US20050232053 Semiconductor integrated circuit device
10/20/2005US20050231867 Electrostatic protection circuit
10/20/2005US20050231864 Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations
10/20/2005US20050231863 Data carrier comprising an integrated circuit with an esd protection circuit
10/20/2005US20050231406 Method and apparatus for selecting multiple settings for an integrated circuit function
10/20/2005US20050231282 Differential output circuit with reduced differential output variation
10/20/2005US20050231268 Threshold voltage detector for process effect compensation
10/20/2005US20050231263 Driver circuit
10/20/2005US20050231262 Semiconductor integrated circuit and a burn-in method thereof
10/20/2005US20050231261 Wide common mode high-speed differential receiver using thin and thick gate oxide MOSFETS in deep-submicron technology
10/20/2005US20050231260 Break before make predriver and level-shifter
10/20/2005US20050231257 Data retaining circuit
10/20/2005US20050231252 Transmission line driver for controlling slew rate and methods thereof
10/20/2005US20050231238 Two-ended voltage level shifter for TFT LCD gate driver
10/20/2005US20050231237 SCL type FPGA with multi-threshold transistors and method for forming same
10/20/2005US20050231236 Routing architecture with high speed I/O bypass path
10/20/2005US20050231235 Programmable logic device having heterogeneous programmable logic blocks
10/20/2005US20050231234 Gate-array or field programmable gate array
10/20/2005US20050231233 Semiconductor integrated circuit device
10/20/2005US20050231231 Shunted current reduction
10/20/2005US20050231230 On-die termination control circuit and method of generating on-die termination control signal
10/20/2005US20050231196 Superconducting driver circuit
10/20/2005US20050230758 Transistor well bias scheme
10/20/2005US20050230751 Semiconductor device
10/19/2005EP1587215A1 Image data transmission circuit and image data display system
10/19/2005EP1303957B1 Digital interface with low power consumption
10/19/2005EP0884599B1 Programming mode selection with jtag circuits
10/19/2005CN2735409Y An improved integrated circuit for digital servo-motor controller
10/19/2005CN1685612A 半导体集成电路 The semiconductor integrated circuit
10/19/2005CN1684368A 输出驱动器电路 Output driver circuit
10/19/2005CN1684358A 带隙参考电路 Bandgap reference circuit
10/19/2005CN1684263A 半导体装置 Semiconductor device
10/19/2005CN1684135A Converting voltage level circuit and method
10/19/2005CN1684050A Semiconductor device and electronic apparatus
10/19/2005CN1224178C Anti noise and burst mode receiving equipment and method for recovering clock signal and its data
10/18/2005US6956920 Apparatus and method for low power routing of signals in a Low Voltage Differential Signaling system
10/18/2005US6956512 Analog-to-digital converter for programmable logic
10/18/2005US6956412 High-voltage input tolerant receiver
10/18/2005US6956404 Driver circuit having a plurality of drivers for driving signals in parallel
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