Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
10/2005
10/05/2005CN1678917A Integrated circuit with embedded identification code
10/05/2005CN1677861A Driver circuit
10/05/2005CN1677860A Level shifter, level shift circuit, electro-optical device, and electronic apparatus
10/05/2005CN1677859A Driver circuit and system including driver circuit
10/05/2005CN1677858A Binary decision picture device
10/05/2005CN1677857A Circuit arrangement for the operation of a switching transistor
10/05/2005CN1677672A 半导体器件 Semiconductor devices
10/04/2005US6952659 Computer system monitoring
10/04/2005US6952370 Data output buffer capable of controlling data valid window in semiconductor memory devices
10/04/2005US6952119 Auxiliary output driver
10/04/2005US6952118 Gate-clocked domino circuits with reduced leakage current
10/04/2005US6952116 Non-cascading charge pump circuit and method
10/04/2005US6952115 Programmable I/O interfaces for FPGAs and other PLDs
10/04/2005US6952114 Apparatus and methods for silicon-on-insulator transistors in programmable logic devices
10/04/2005US6952113 Method of reducing leakage current in sub one volt SOI circuits
10/04/2005US6952112 Output buffer circuit with control circuit for modifying supply voltage and transistor size
09/2005
09/29/2005WO2005091505A1 Programming matrix
09/29/2005WO2005091504A1 Reconfigurable digital logic unit
09/29/2005US20050213781 Charge pump circuit
09/29/2005US20050213757 Decryption circuit, encryption circuit, logic cell, and method of performing a dual-rail logic operation in single-rail logic environment
09/29/2005US20050213416 Semiconductor circuit apparatus with power save mode
09/29/2005US20050213414 Semiconductor integrated circuit device having power reduction mechanism
09/29/2005US20050212581 Radio frequency CMOS buffer circuit and method
09/29/2005US20050212578 Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design program
09/29/2005US20050212567 High voltage CMOS switch with reduced high voltage junction stresses
09/29/2005US20050212563 Efficient detection of multiple assertions in a bus
09/29/2005US20050212562 Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone
09/29/2005US20050212561 Apparatus and method for a low jitter predriver for differential output drivers
09/29/2005US20050212560 Semiconductor integrated circuit device operating with low power consumption
09/29/2005US20050212559 Single-ended to differential conversion circuit with duty cycle correction
09/29/2005US20050212558 Thin-oxide devices for high voltage I/O drivers
09/29/2005US20050212557 Level-conversion circuit
09/29/2005US20050212556 Programmable logic device with high speed serial interface circuitry
09/29/2005US20050212555 Semiconductor circuit
09/29/2005US20050212554 Leakage current reduction method
09/29/2005US20050212553 Method and apparatus for selectably providing single-ended and differential signaling with controllable impedence and transition time
09/29/2005US20050212552 Semiconductor integrated circuit device and on-die termination circuit
09/29/2005US20050212551 Memory module system with efficient control of on-die termination
09/29/2005US20050212550 Semiconductor device incorporating characteristic evaluating circuit operated by high frequency clock signal
09/29/2005DE102004011487A1 Logic basic cell e.g. field programmable gate array, for use in logic device, has four data signal inputs selectable by respective n-MOS selection transistors, which are provided between respective signal inputs
09/29/2005DE102004010890A1 Verfahren und Schaltungsanordnung zum Umschalten eines elektrischen Schaltkreises in einen Stromsparmodus Method and circuit for switching an electrical circuit in a power saving mode
09/29/2005DE102004001669A1 Konfigurierbares Logikbauelement ohne lokalen Konfigurationsspeicher mit parallelem Konfigurationsbus Configurable logic device without local configuration memory with parallel configuration bus
09/28/2005EP1580890A1 Low voltage driver
09/28/2005EP1580874A2 Method and apparatus for robust mode selection with low power consumption
09/28/2005EP1579574A1 Ac powered logic circuitry
09/28/2005EP1579494A1 N-channel pull-up element logic circuit
09/28/2005EP1579226A2 System with multiple path fail over, fail back and load balancing
09/28/2005EP1238460B1 Magnetic logic device having magnetic quantum dots
09/28/2005CN1674444A 电荷泵电路 The charge pump circuit
09/28/2005CN1674443A Level-conversion circuit
09/28/2005CN1674442A Level conversion circuit and serial/parallel conversion circuit with level conversion function
09/28/2005CN1674441A Source electrode drive circuit, latch voltage bit quasi converter and high voltage positive and negative device
09/28/2005CN1674440A Dynamic multi-input priority multiplexer and method for selecting signal
09/28/2005CN1674254A Special semiconductor circuit and resource configuration method for semiconductor circuit driver
09/28/2005CN1674154A Clock stop detector
09/28/2005CN1221079C Universal bi-directional digital signal electric separator
09/28/2005CN1220952C Dispersive bus terminal framework
09/27/2005US6950970 Operation report creation system, operation report creation method, and operation report creation program
09/27/2005US6949970 Voltage standard apparatus
09/27/2005US6949964 Sub-micron high input voltage tolerant input output (I/O) circuit
09/27/2005US6949963 Line driver with current source output and high immunity to RF signals
09/27/2005US6949957 Command user interface with programmable decoder
09/27/2005US6949956 General purpose delay logic
09/27/2005US6949955 Synchronizing signals between clock domains
09/27/2005US6949954 Method and apparatus for an asynchronous pulse logic circuit
09/27/2005US6949951 Integrated circuit multiplexer including transistors of more than one oxide thickness
09/27/2005US6949949 Apparatus and method for adjusting the impedance of an output driver
09/27/2005US6949948 Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges
09/27/2005US6949947 Test mode circuit of semiconductor device
09/22/2005WO2005088839A1 Programmable logic array for schedule-controlled processing
09/22/2005WO2005088838A1 Logic basic cell, logic basic cell array and logic device
09/22/2005WO2005086746A2 Programmable-logic acceleraton of data processing applications
09/22/2005US20050208902 Signal transmission circuit, signal output circuit and termination method of signal transmission circuit
09/22/2005US20050207504 Signal transmission circuit
09/22/2005US20050207240 Digital processing device with disparate magnetoelectronic gates
09/22/2005US20050206640 Image display panel and level shifter
09/22/2005US20050206602 Driving voltage generation device and method for controlling driving voltage generation device
09/22/2005US20050206585 Display devices and integrated circuits
09/22/2005US20050206536 Cross-bar matrix with LCD functionality
09/22/2005US20050206432 Level conversion circuit and serial/parallel conversion circuit with level conversion function
09/22/2005US20050206431 Circuit for transforming signals varying between different voltages
09/22/2005US20050206423 Latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits
09/22/2005US20050206415 Programmable phase-locked loop circuitry for programmable logic device
09/22/2005US20050206411 Device for generating a bit line selection signal of a memory device
09/22/2005US20050206410 Clock stop detector
09/22/2005US20050206409 Enhanced cmos circuit to drive dc motors
09/22/2005US20050206407 Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
09/22/2005US20050206406 Programmable function generator and method operating as combinational, sequential and routing cells
09/22/2005US20050206405 Method and apparatus of memory clearing with monitoring ram memory cells in a field programmable gated array
09/22/2005US20050206324 Input/output buffer
09/22/2005DE102005009525A1 Optischer Logikbaustein Optical logic device
09/22/2005DE102004009144A1 Schaltung Circuit
09/21/2005EP1577789A2 Reconfigurable circuit with connection unit
09/21/2005CN1670862A Device for generating a bit line selection signal of a memory device
09/21/2005CN1670688A Universal integrated circuit for balance comparator and linear stepping motor
09/21/2005CN1670597A Image display panel and level shifter
09/21/2005CN1670469A 传感器控制器 Sensor Controller
09/20/2005US6947882 Regionally time multiplexed emulation system
09/20/2005US6947859 Dynamic current calibrated driver circuit
09/20/2005US6947336 Semiconductor device with impedance control circuit
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