Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
05/2005
05/18/2005CN1202635C Circuit and method for simultaneously multi-way transmit multiple signal between multiple circuits
05/18/2005CN1202619C I/O buffer with protective circuit worked on multilevel voltage
05/17/2005US6895570 System and method for optimizing routing lines in a programmable logic device
05/17/2005US6895534 Systems and methods for providing automated diagnostic services for a cluster computer system
05/17/2005US6894921 Standard cell arrangement for a magneto-resistive component
05/17/2005US6894549 Ferroelectric non-volatile logic elements
05/17/2005US6894547 Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit
05/17/2005US6894545 Integrated circuit
05/17/2005US6894543 Series terminated CMOS output driver with impedance calibration
05/17/2005US6894538 Expanding module for serial transmission
05/17/2005US6894534 Dynamic programmable logic array that can be reprogrammed and a method of use
05/17/2005US6894533 Interconnection and input/output resources for programmable logic integrated circuit devices
05/17/2005US6894531 Interface for a programmable logic device
05/17/2005US6894530 Programmable and fixed logic circuitry for high-speed interfaces
05/17/2005US6894529 Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control
05/17/2005US6894528 Process monitor based keeper scheme for dynamic circuits
05/17/2005US6894527 Evolved circuits for bitstream protection
05/17/2005US6894501 Selecting multiple settings for an integrated circuit function using a single integrated circuit terminal
05/12/2005WO2005043761A1 Circuit system
05/12/2005WO2005027444A3 Tx line driver with common mode idle state and selectable slew rates
05/12/2005WO2005010943A3 High side power switch with charge pump and bootstrap capacitor
05/12/2005WO2005008891A3 Columnar architecture for pla or fpga
05/12/2005US20050102646 Configuration circuits for three dimensional programmable logic devices
05/12/2005US20050102573 In-circuit configuration architecture for embedded configurable logic array
05/12/2005US20050100046 Cross-level digital signal transmission devic
05/12/2005US20050099858 Encoding circuit for semiconductor device and redundancy control circuit using the same
05/12/2005US20050099843 Low current wide VREF range input buffer
05/12/2005US20050099842 Low current wide VREF range input buffer
05/12/2005US20050099413 Method of resetting a shut down integrated circuit spontaneously and the monitor thereof
05/12/2005US20050099219 Setting multiple chip parameters using one IC terminal
05/12/2005US20050099218 System including an integrated circuit memory device having an adjustable output voltage setting
05/12/2005US20050099207 Low leakage ioff and overvoltage ioz circuit
05/12/2005US20050099206 CMOS to PECL voltage level converter
05/12/2005US20050099205 Register-file bit-read method and apparatus
05/12/2005US20050099068 Digital circuit having correcting circuit and electronic apparatus thereof
05/12/2005US20050098743 Input circuit apparatus
05/11/2005EP1530293A2 Voltage controlled oscillator circuit
05/11/2005EP1529343A1 Circuit and method for controlling the threshold voltage of transistors
05/11/2005CN1615587A Integrated circuit and battery powered electronic device
05/11/2005CN1614891A Gate controlling circuit for raising transistor with nigh voltage input
05/11/2005CN1201489C Electronic circuit
05/11/2005CN1201264C Power supply circuit building in integrated circuit
05/10/2005US6891708 Reduced current and power consumption structure of drive circuit
05/10/2005US6891422 Level shifter and flat panel display
05/10/2005US6891398 Skewed falling logic device for rapidly propagating a falling edge of an output signal
05/10/2005US6891397 Gigabit router on a single programmable logic device
05/10/2005US6891396 Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
05/10/2005US6891394 Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
05/06/2005WO2005041411A1 Dynamic cycles and sequencers, based on binary trees with magnetic nodes, the rapidity of execution, the operating reliability and the durability of use of which are optimised
05/06/2005WO2005041202A1 Random access memory having self-adjusting off-chip driver
05/06/2005WO2005008775A3 Columnar architecture for pla or fpga
05/06/2005WO2004105245A3 Half-swing line precharge method and apparatus
05/06/2005WO2004077260A3 Method and apparatus for creating circuit redundancy in programmable logic devices
05/05/2005US20050097499 In-circuit configuration architecture with non-volatile configuration store for embedded configurable logic array
05/05/2005US20050097496 High-speed and low-power logical unit
05/05/2005US20050094654 Switching matrix
05/05/2005US20050094473 Semiconductor integrated circuits with power reduction mechanism
05/05/2005US20050093620 Integrated circuit and method for interfacing two voltage domains using a transformer
05/05/2005US20050093585 CMOS output buffer circuit
05/05/2005US20050093579 LVDS driver circuit and driver circuit
05/05/2005US20050093578 Output device for static random access memory
05/05/2005US20050093576 Three-transistor nand and nor gates for two-phase clock generators
05/05/2005US20050093574 Control circuit and reconfigurable logic block
05/05/2005US20050093573 Semiconductor devices fabricated with different processing options
05/05/2005US20050093572 In-circuit configuration architecture with configuration on initialization function for embedded configurable logic array
05/05/2005US20050093571 Memory re-implementation for field programmable gate arrays
05/05/2005US20050093570 Integrated line driver
05/05/2005US20050093569 Pseudodynamic off-chip driver calibration
05/04/2005EP1528684A2 Programmable phase-locked loop circuitry for programmable logic device
05/04/2005EP1528682A1 Method and apparatus for mode selection for high voltage integrated circuits
05/04/2005EP1528681A1 Microelectronic circuit for activating or deactivating at least one input/output, corresponding chip card reader and method of deactivating
05/04/2005EP1527457A2 Memory cells enhanced for resistance to single event upset
05/04/2005CN2697951Y High-speed current mode logic circuit chip
05/04/2005CN1613184A Probabilistic calculation element, drive method thereof, and recognition device using the same
05/04/2005CN1613183A LVDS driver for small supply voltages
05/04/2005CN1612481A Pseudodynamic off-chip driver calibration
05/04/2005CN1612002A Output circuit, digital analog circuit and display device
05/04/2005CN1200516C 负电压电平转换电路 Negative voltage level conversion circuit
05/04/2005CN1200515C 负电压译码电路 Negative voltage decoding circuit
05/04/2005CN1200514C Output buffering device and method
05/04/2005CN1200432C 电荷泵电路 The charge pump circuit
05/04/2005CN1200393C Integrated circuit and circuit arrangement for supplying intergrated circuit with electricity
05/03/2005US6888765 Integrated circuit and method for testing same using single pin to control test mode and normal mode operation
05/03/2005US6888746 Magnetoelectronic memory element with inductively coupled write wires
05/03/2005US6888395 Semiconductor integrated circuit device
05/03/2005US6888392 Method and related circuitry for buffering output signals of a chip with even number driving circuits
05/03/2005US6888378 Semiconductor integrated circuit
05/03/2005US6888377 Duo-mode keeper circuit
05/03/2005US6888376 Multiple data rates in programmable logic device serial interface
05/03/2005US6888375 Tileable field-programmable gate array architecture
05/03/2005US6888374 FPGA peripheral routing with symmetric edge termination at FPGA boundaries
05/03/2005US6888373 Fracturable incomplete look up table for area efficient logic elements
05/03/2005US6888372 Programmable logic device with soft multiplier
05/03/2005US6888371 Programmable interface for field programmable gate array cores
05/03/2005US6888370 Dynamically adjustable termination impedance control techniques
05/03/2005US6888369 Programmable on-chip differential termination impedance
05/03/2005US6888202 Low-power high-performance storage circuitry
04/2005
04/28/2005WO2005038592A2 System and method for dynamically executing a function in a programmable logic array
04/28/2005US20050091630 Programmable interconnect structures
04/28/2005US20050091624 Molecular logic gates
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