| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 07/13/2005 | CN1210869C 半导体器件 Semiconductor devices |
| 07/13/2005 | CN1210155C Printing head substrate, printing head and printing equipment |
| 07/12/2005 | US6918124 Query trees including or nodes for event filtering |
| 07/12/2005 | US6918052 Managing operations of a computer system having a plurality of partitions |
| 07/12/2005 | US6917546 Memory device and memory system |
| 07/12/2005 | US6917239 Level shift circuit and semiconductor device |
| 07/12/2005 | US6917236 Method and apparatus for level shifting |
| 07/12/2005 | US6917235 Low voltage circuit for interfacing with high voltage analog signals |
| 07/12/2005 | US6917226 Transformer coupling arrangement and method using a plurality of drivers |
| 07/12/2005 | US6917222 Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges and systems including same |
| 07/12/2005 | US6917221 Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits |
| 07/12/2005 | US6917220 Semiconductor device and a method for checking state transition thereof |
| 07/12/2005 | US6917082 Gate-body cross-link circuitry for metal-oxide-semiconductor transistor circuits |
| 07/12/2005 | US6917074 Multiplexer structure with interdigitated gates and shared diffusion |
| 07/12/2005 | US6916719 Method and apparatus for non-conductively interconnecting integrated circuits |
| 07/07/2005 | WO2005062470A1 Gray code counter |
| 07/07/2005 | WO2005062469A1 Noise-tolerant signaling schemes supporting simplified timing and data recovery |
| 07/07/2005 | WO2005062468A2 An output drive circuit that accommodates variable supply voltages |
| 07/07/2005 | WO2005062212A1 Template-based domain-specific reconfigurable logic |
| 07/07/2005 | WO2005006556A3 Integrated circuit with interface tile for coupling to a stacked -die second integrated circuit |
| 07/07/2005 | WO2005006443A8 Logic gate with a potential-free gate electrode for organic integrated circuits |
| 07/07/2005 | WO2005006392A3 Low voltage circuit for interfacing with high voltage analog signals |
| 07/07/2005 | WO2004044952A3 Integrated circuit with automatic pin-strapping configuration |
| 07/07/2005 | WO2004032323A3 Circuit arrangement for bridging high voltages using a switching signal |
| 07/07/2005 | US20050149896 Integrated circuits with RAM and ROM fabrication options |
| 07/07/2005 | US20050149659 Apparatus and method for topography dependent signaling |
| 07/07/2005 | US20050147178 Data transfer system and method, data transmitter, data receiver, data transmission method, and data reception method |
| 07/07/2005 | US20050146971 Semiconductor circuit device having active and standby states |
| 07/07/2005 | US20050146953 Semiconductor integrated circuit device |
| 07/07/2005 | US20050146922 Logical operation circuit and logical operation method |
| 07/07/2005 | US20050146829 Using feedback to select transmitting voltage |
| 07/07/2005 | US20050146819 Circuit output stage protection system |
| 07/07/2005 | US20050146374 Semiconductor integrated circuit device |
| 07/07/2005 | US20050146358 Avoiding oscillation in self-synchronous bi-directional communication system |
| 07/07/2005 | US20050146357 Encoder and decoder circuits for dynamic bus |
| 07/07/2005 | US20050146356 Driver circuit |
| 07/07/2005 | US20050146354 Multi-level routing architecture in a field programmable gate array having transmitters and receivers |
| 07/07/2005 | US20050146352 Look-up table based logic macro-cells |
| 07/07/2005 | US20050146351 Self-rewinding circuit |
| 07/07/2005 | US20050146350 Impedance controller and impedance control method |
| 07/07/2005 | DE10357209A1 Basic logic cell for programmable logic device combining two data signals according to logic function selectable by numerous logic selection elements, with four data signal inputs for two data signals, their complementary data signals |
| 07/07/2005 | DE10356851A1 Shift register for configuring bits used to program logic circuits, includes master- and slave latches with analysis logic to output configuration bits |
| 07/07/2005 | DE102004056231A1 NAND logic gate comprises quantum wire transistor controlled by side gates |
| 07/06/2005 | EP1550950A1 Semiconductor device |
| 07/06/2005 | EP1550192A1 System and method for application monitoring and automatic disaster recovery for high-availability |
| 07/06/2005 | EP1550149A2 Constant delay zero standby differential logic receiver and method |
| 07/06/2005 | CN1636366A Apparatus and method for power efficient line driver |
| 07/06/2005 | CN1636320A Integrated circuit having reduced substate bounce |
| 07/06/2005 | CN1636185A Logic computing system and method |
| 07/06/2005 | CN1209877C Appts. and method for generating electromigration |
| 07/06/2005 | CN1209876C Low operation voltage level shifter completed by thin film transistor |
| 07/06/2005 | CN1209875C Buffer capable of regulating duty ratio and its operation method |
| 07/06/2005 | CN1209874C Low voltage differential signal transmission device |
| 07/05/2005 | US6915459 Active failsafe detection for differential receiver circuits |
| 07/05/2005 | US6915323 Macrocells supporting a carry cascade |
| 07/05/2005 | US6914807 Magnetic logic element and magnetic logic element array |
| 07/05/2005 | US6914804 Memory cells enhanced for resistance to single event upset |
| 07/05/2005 | US6914470 Level shifting circuit |
| 07/05/2005 | US6914467 Dual edge programmable delay unit |
| 07/05/2005 | US6914456 Sub-micron high input voltage tolerant input output (I/O) circuit |
| 07/05/2005 | US6914453 Integrated logic and latch design with clock gating at static input signals |
| 07/05/2005 | US6914452 Adaptive keeper sizing for dynamic circuits based on fused process corner data |
| 07/05/2005 | US6914451 Adaptive level binary logic |
| 07/05/2005 | US6914450 Register-file bit-read method and apparatus |
| 07/05/2005 | US6914449 Structure for reducing leakage current in submicron IC devices |
| 06/30/2005 | WO2005060193A2 High speed signaling system with adaptive transmit pre-emphasis, reflection cancellation and offset cancellation |
| 06/30/2005 | WO2005060102A1 Level shift circuit, actuator apparatus using the same, and optical switch system |
| 06/30/2005 | US20050144539 Semiconductor device capable of preventing malfunction resulting from false signal generated in level shift circuit |
| 06/30/2005 | US20050144212 Programmable logic device with cascading DSP slices |
| 06/30/2005 | US20050144211 Programmable logic device with pipelined DSP slices |
| 06/30/2005 | US20050144210 Programmable logic device with dynamic DSP architecture |
| 06/30/2005 | US20050143022 Wireless programmable logic devices |
| 06/30/2005 | US20050140430 Programmable AC current booster for faster edge-rate output in high speed applications |
| 06/30/2005 | US20050140424 Receiving device |
| 06/30/2005 | US20050140421 Level shifter and flat panel display |
| 06/30/2005 | US20050140414 Delay circuit and display including the same |
| 06/30/2005 | US20050140413 Driving device using CMOS inverter |
| 06/30/2005 | US20050140394 Semiconductor integrated circuit device and differential small-amplitude data transmission apparatus |
| 06/30/2005 | US20050140393 High-speed transmitter circuit |
| 06/30/2005 | US20050140392 Circuit for eliminating leakage current in signal transmission |
| 06/30/2005 | US20050140391 Method utilizing a one-stage level shift circuit |
| 06/30/2005 | US20050140390 Finite state machine circuit |
| 06/30/2005 | US20050140389 Logic basic cell and logic basic cell arrangement |
| 06/30/2005 | DE10354501A1 Logik-Schaltkreis-Anordnung Logic circuit arrangement |
| 06/30/2005 | DE10352812A1 Signal-generating method for ternary signals produces signal levels and coupled potentials by triggering switching devices |
| 06/30/2005 | DE102004056322A1 Digital logic base module structure uses units having logic blocks coupled to multiplexing stages |
| 06/30/2005 | DE102004016978A1 Control circuit for use with output driver, has amplifier circuit to adjust phase voltage level of output signal from output driver, and resistance circuit to adjust control voltage level of control signal based on resistance value |
| 06/29/2005 | EP1548944A2 Receiving device |
| 06/29/2005 | EP1548943A1 ECL to CMOS converter |
| 06/29/2005 | EP1548702A1 Method for ultra-fast controlling of a magnetic cell and related devices |
| 06/29/2005 | EP1547248A2 High speed zero dc power programmable logic device (pld) architecture |
| 06/29/2005 | EP1546947A2 Method and system for debugging using replicated logic |
| 06/29/2005 | EP0961980B1 Method for self-synchronization of configurable elements of a programmable component |
| 06/29/2005 | CN1632767A System and method for loading on-site programmable gate array |
| 06/29/2005 | CN1208900C Computing circuit |
| 06/29/2005 | CN1208628C Apparatus and method for programmable parametric toggle testing of digital CMOS pads |
| 06/28/2005 | US6912139 Multi-channel control methods for switched power converters |
| 06/28/2005 | US6912132 Support module ejection mechanism |
| 06/28/2005 | US6911855 Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process |
| 06/28/2005 | US6911847 Current switching type of high-speed logic circuit which generates output pair of differential signals each having accurately matched rise-time and fall-time waveform characteristics |