Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
06/2005
06/16/2005US20050127946 Pipeline-based circuit with a postponed clock-gating mechanism for reducing power consumption and related driving method thereof
06/16/2005US20050127945 Data inversion circuits having a bypass mode of operation and methods of operating the same
06/16/2005US20050127944 Versatile logic element and logic array block
06/16/2005US20050127943 Method and device for configuration of PLDs
06/16/2005US20050127941 Semiconductor device
06/16/2005US20050127940 Signal transmitting device suited to fast signal transmission
06/16/2005US20050127939 Output buffer compensation control
06/16/2005US20050127938 Bus agent having multiple reference levels
06/16/2005US20050127937 Integrated circuit with reduced body effect sensitivity
06/16/2005US20050127404 Basic cells configurable into different types of semiconductor integrated circuits
06/16/2005US20050126543 Drive device for electrical injectors of an internal combustion engine common rail fuel injection system
06/15/2005EP1542365A1 Dynamic logic return-to-zero latching circuit
06/15/2005EP1542364A1 Dynamic logic register
06/15/2005EP1540659A1 A method and a unit for programming a memory
06/15/2005EP1540507A2 Methods and devices for treating and/or processing data
06/15/2005EP1105968A4 Current-controlled output buffer
06/15/2005CN1628416A Input stage resistant against high voltage swings
06/15/2005CN1628415A Digital electronic circuit with low power consumption
06/15/2005CN1627644A Circuit and associated methodology
06/15/2005CN1627643A Bit order converter
06/15/2005CN1627500A Single supply level converter
06/15/2005CN1627437A Memory device
06/15/2005CN1627232A 半导体装置 Semiconductor device
06/15/2005CN1206809C 直流电平转换器 DC level converter
06/14/2005US6907592 Method of routing in a programmable logic device
06/14/2005US6907585 Semiconductor integrated circuit and its design methodology
06/14/2005US6906965 Temperature-compensated output buffer circuit
06/14/2005US6906575 Semiconductor integrated circuit device
06/14/2005US6906567 Method and structure for dynamic slew-rate control using capacitive elements
06/14/2005US6906561 Cascode stage input/output device
06/14/2005US6906556 High-speed domino logic with improved cascode keeper
06/14/2005US6906554 Pipeline-based circuit with a postponed clock-gating mechanism for reducing power consumption and related driving method thereof
06/14/2005US6906553 Circuitry for providing overvoltage backdrive protection
06/14/2005US6906552 System and method utilizing a one-stage level shift circuit
06/14/2005US6906550 Modable dynamic terminator for high speed digital communications
06/14/2005US6906426 Transceiver having shadow memory facilitating on-transceiver collection and communication of local parameters
06/14/2005US6906388 SEU hard majority voter for triple redundancy
06/09/2005WO2005053157A2 Multistage dynamic domino circuit with internally generated delay reset clock
06/09/2005US20050125760 Data processing in digital systems
06/09/2005US20050125642 Dynamically reconfigurable logic circuit device, interrupt control method, and semi-conductor integrated circuit
06/09/2005US20050122807 Microelectronic circuit for activation of deactivation of at least one input/output, corresponding smart card reader and deactivation method
06/09/2005US20050122758 Field programmable gate array incorporating dedicated memory stacks
06/09/2005US20050122611 Semiconductor device and a disk drive apparatus employing such a semiconductor device
06/09/2005US20050122175 Oscillator circuit operating with a variable driving voltage
06/09/2005US20050122156 Level-shifting circuitry having "high" output impedance during disable mode
06/09/2005US20050122155 Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit
06/09/2005US20050122154 Bi-directional signal level shift circuit
06/09/2005US20050122151 Dual edge programmable delay unit
06/09/2005US20050122142 Circuit for controlling internal supply voltage driver
06/09/2005US20050122141 Driver-side current clamping with non-persistent charge boost
06/09/2005US20050122136 Methods and arrangements for an enhanced scanable latch circuit
06/09/2005US20050122135 Chip to chip interface
06/09/2005US20050122132 Configuration memory implementation for lut-based reconfigurable logic architectures
06/09/2005US20050122131 Termination enable: hardware and software controlled enable with detect
06/09/2005US20050122130 Methods and apparatus for active termination of high-frequency signals
06/09/2005US20050122129 Connected transistors; delay circuit; power sources
06/09/2005US20050121698 FPGA blocks with adjustable porosity pass thru
06/09/2005DE10351016B3 Pseudo-dynamische Off-Chip-Treiber-Kalibrierung Pseudo-dynamic off-chip driver calibration
06/09/2005DE102004053675A1 Eingangsschaltung Input circuit
06/08/2005EP1537667A2 Event driven dynamic logic for reducing power consumption
06/08/2005EP1537666A2 Supply voltage modulation circuit for mos transistors, reconfigurable logic device and method of processing an input signal to a logic circuit
06/08/2005EP1537663A2 Transition detection at input of integrated circuit device
06/08/2005EP1537426A2 Integrated circuit with embedded identification code
06/08/2005EP1461861A4 Hot carrier injection suppression circuit
06/08/2005EP0935850B1 System connector
06/08/2005CN1625899A Digital video processing devices
06/08/2005CN1625838A Logical operation circuit and logical operation method
06/08/2005CN1625837A Logical operation circuit and logical operation method
06/08/2005CN1625054A Dual edge programmable delay unit and method for providing programm of the unit
06/08/2005CN1624805A Shift register of safety providing configuration bit
06/08/2005CN1205750C High-speed data buffer
06/08/2005CN1205617C Buff circuit
06/08/2005CN1205519C Low power voltage regulator circuit for use ni integrated circuit device
06/07/2005US6904576 Method and system for debugging using replicated logic
06/07/2005US6904478 Transceiver interface reduction
06/07/2005US6904447 High speed low power 4-2 compressor
06/07/2005US6904116 Shift register
06/07/2005US6903588 Slew rate controlled output buffer
06/07/2005US6903581 Output buffer for high and low voltage bus
06/07/2005US6903579 Pipelined low-voltage current-mode logic with a switching stack height of one
06/07/2005US6903575 Scalable device architecture for high-speed interfaces
06/07/2005US6903574 Memory access via serial memory interface
06/07/2005US6903573 Programmable logic device with enhanced wide input product term cascading
06/07/2005US6903572 Switch matrix circuit, logical operation circuit, and switch circuit
06/07/2005US6903571 Programmable systems and devices with multiplexer circuits providing enhanced capabilities for triple modular redundancy
06/07/2005US6903570 Bidirectional signal transmission circuit
06/07/2005US6903569 Input terminal with combined logic threshold and reset function
06/02/2005WO2005050936A1 Power savings in serial link transmitters
06/02/2005WO2005050847A1 A device for processing a signal
06/02/2005WO2005013324A3 Memory access via serial memory interface
06/02/2005US20050120324 Integrated circuit designing support apparatus and method for the same
06/02/2005US20050120323 Method for modifying the behavior of a state machine
06/02/2005US20050117436 Logic array devices having complex macro-cell architecture and methods facilitating use of same
06/02/2005US20050117394 Switch matrix circuit, logical operation circuit, and switch circuit
06/02/2005US20050116765 Semiconductor integrated circuit
06/02/2005US20050116752 Output buffer with adjustment of signal transitions
06/02/2005US20050116746 Input buffer for detecting an input signal
06/02/2005US20050116739 Method and circuit for element wearout recovery
06/02/2005US20050116736 Method and circuit for off chip driver control, and memory device using same
06/02/2005US20050116735 Partial termination voltage current shunting
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