Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
11/2005
11/24/2005US20050259497 Internal voltage generator scheme and power management method
11/24/2005US20050259484 Systems and methods for write protection of non-volatile memory devices
11/24/2005US20050258997 Analog buffer, display device having the same, and method of driving the same
11/24/2005US20050258887 Level shifter having automatic delay adjusting function
11/24/2005US20050258886 Voltage level conversion circuit
11/24/2005US20050258876 System for producing high-voltage, low-power driver circuitry
11/24/2005US20050258875 Pre-driver circuit
11/24/2005US20050258873 Current-controlled CMOS circuits with inductive broadbanding
11/24/2005US20050258872 Architecture and methods for computing with reconfigurable resistor crossbars
11/24/2005US20050258871 Electronic circuit with a differential pair of transistors and logic gate comprising such a circuit
11/24/2005US20050258870 Precompensated driver with constant impedance
11/24/2005US20050258869 Balanced line output stage circuit providing reduced electromagnetic interference
11/24/2005US20050258868 Transmission circuit, data-transfer control device and electronic equipment
11/24/2005US20050258867 Electronic circuit, electro-optical device, electronic device and electronic apparatus
11/24/2005US20050258866 Integrated circuit with breakdown voltage multiplier
11/24/2005US20050258865 System, method and program product for extending range of a bidirectional data communication bus
11/24/2005US20050258864 Integrated circuit for level-shifting voltage levels
11/24/2005US20050258863 Quaternary and trinary logic switching circuits
11/24/2005US20050258862 Apparatus and methods for adjusting performance of programmable logic devices
11/24/2005US20050258860 Output buffer circuit with control circuit for modifying supply voltage and transistor size
11/24/2005US20050258495 Gate driver output stage with bias circuit for high and wide operating voltage range
11/24/2005US20050257947 Integrated circuit having building blocks
11/24/2005DE102005018736A1 Versorgungsleitungsanordnung, Off-Chip-Treiberanordnung und Halbleiterschaltungsmodul Supply line assembly, off-chip driver assembly and semiconductor circuit module
11/24/2005DE102005018640A1 Schaltungsmodul Circuit module
11/24/2005DE102005018114A1 Spannungs-/Prozessbewertung bei Halbleitern Voltage / process evaluation in semiconductors
11/23/2005EP1598937A2 Circuit with at least one delay cell
11/23/2005EP1598834A2 Nanomagnetic materials
11/23/2005EP1598747A2 Programmable configuration integrated circuit
11/23/2005EP1597826A1 Electronic circuit with array of programmable logic cells
11/23/2005EP1597825A2 Electronic circuit with array of programmable logic cells
11/23/2005CN1701511A 半导体装置 Semiconductor device
11/23/2005CN1700601A Logic circuit apparatus
11/23/2005CN1700600A Voltage level conversion circuit
11/23/2005CN1700599A 半导体器件 Semiconductor devices
11/23/2005CN1700285A Electronic circuit, electro-optical device, electronic device and electronic apparatus
11/23/2005CN1228848C Electronic circuit and semiconductor memory
11/22/2005US6968523 Design method of logic circuit using data flow graph
11/22/2005US6968487 User available body scan chain
11/22/2005US6968486 Master-slave-type scanning flip-flop circuit for high-speed operation with reduced load capacity of clock controller
11/22/2005US6968475 Generalized pre-charge clock circuit for pulsed domino gates
11/22/2005US6968452 Method of self-synchronization of configurable elements of a programmable unit
11/22/2005US6968218 Method and apparatus for electrically coupling digital devices
11/22/2005US6967881 Semiconductor integrated circuit and method of manufacturing of semiconductor integrated circuit
11/22/2005US6967591 Multi-bit digital input using a single pin
11/22/2005US6967518 High voltage level shifting IC with under-ground voltage swing withstanding capability
11/22/2005US6967515 Single-ended to differential conversion circuit with duty cycle correction
11/22/2005US6967514 Method and apparatus for digital duty cycle adjustment
11/22/2005US6967512 Multiphase-clock processing circuit and clock multiplying circuit
11/22/2005US6967510 Time-base implementation for correcting accumulative error with chip frequency scaling
11/22/2005US6967505 Input circuit
11/22/2005US6967504 Differential output circuit for improving bandwidth
11/22/2005US6967502 Dynamic circuit
11/22/2005US6967501 Impedance-matched output driver circuits having enhanced predriver control
11/22/2005US6967381 Semiconductor device
11/22/2005US6967378 Semiconductor integrated circuit device configured to prevent the generation of a reverse current in a MOS transistor
11/17/2005WO2005109646A1 Integrated circuit having multidimensional switch topology
11/17/2005WO2005109616A1 Pwm driver circuit
11/17/2005WO2005109462A2 Apparatus and method for shifting a signal from a first reference level to a second reference level
11/17/2005WO2005066821A3 Using feedback to select transmitting voltage
11/17/2005WO2005036353A8 Method and apparatus for a chaotic computing module
11/17/2005WO2004100376A9 Buffer circuit
11/17/2005US20050257177 System on chip development with reconfigurable multi-project wafer technology
11/17/2005US20050257031 Field programmable gate array and microcontroller system-on-a-chip
11/17/2005US20050257030 Programmable logic integrated circuit devices including dedicated processor components and hard-wired functional units
11/17/2005US20050257024 Loosely-biased heterogeneous reconfigurable arrays
11/17/2005US20050256007 Adiabatic quantum computation with superconducting qubits
11/17/2005US20050254326 Semiconductor integrated circuit for reducing crosstalk and method for designing the same
11/17/2005US20050254314 Voltage generator
11/17/2005US20050253746 Superconducting multi-stage sigma-delta modulator
11/17/2005US20050253661 Oscillator circuit for semiconductor device
11/17/2005US20050253641 Circuit with at least one delay cell
11/17/2005US20050253640 Control signal generator, latch circuit, flip-flop and method for controlling operations of the flip-flop
11/17/2005US20050253627 Multi level fixed parameter assignment
11/17/2005US20050253626 Supply voltage detection circuit
11/17/2005US20050253625 Logic basic cell, logic basic cell arrangement and logic device
11/17/2005US20050253624 Apparatus and method adapted to use one-time programming devices for multiple-time programming
11/17/2005US20050253623 System generated electromagnetic pulse guard
11/17/2005US20050253621 Method and topology for improving signal quality on high speed, multi-drop busses
11/17/2005US20050253571 MEMS waveform generator and adiabatic logic circuits using the same
11/17/2005US20050253256 Supply line arrangement, off chip driver arrangement, and semiconductor circuitry module
11/17/2005DE202005011860U1 Trinary full subtracter circuit for digital computers has half-adder and half-subtracter with OR gate interconnected for generation of output whereby different potential levels are represented by different logical numbers
11/17/2005DE19825258B4 Ausgangspufferschaltkreis zum Übertragen von digitalen Signalen über eine Übertragungsleitung mit Preemphasis An output buffer circuit for transmitting digital signals over a transmission line with preemphasis
11/17/2005DE102005015001A1 Schwellenspannungsdetektor zur Prozesseffektkompensation Threshold voltage detector for process effect compensation
11/17/2005DE102004018976A1 Verbesserte Gate-Array oder FPGA Improved gate array or FPGA
11/16/2005EP1297629B1 Buffer with compensating drive strength
11/16/2005EP1240054B1 Circuit for activating a can (car area network) bus control unit
11/16/2005CN1698268A Semiconductor integrated circuit
11/16/2005CN1697180A Semiconductor integrated circuit for reducing crosstalk and method for designing the same
11/16/2005CN1227814C Switching aid circuit for a logic circuit
11/16/2005CN1227813C Synchronous charge-pumped noise cancellation device, system and method
11/16/2005CN1227740C Semiconductor integrated circuit
11/15/2005US6966046 CMOS tapered gate and synthesis method
11/15/2005US6966044 Method for composing memory on programmable platform devices to meet varied memory requirements with a fixed set of resources
11/15/2005US6965845 Method and apparatus for system management using codebook correlation with symptom exclusion
11/15/2005US6965264 Adaptive threshold scaling circuit
11/15/2005US6965253 Reduced-capacitance bus switch in isolated P-well shorted to source and drain during switching
11/15/2005US6965252 Power saving methods for programmable logic arrays
11/15/2005US6965251 Input buffer with hysteresis option
11/15/2005US6965250 Reduced delay power fail-safe circuit
11/15/2005US6965249 Programmable logic device with redundant circuitry
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