Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
03/2005
03/08/2005US6864713 Multi-stage interconnect architecture for complex programmable logic devices
03/08/2005US6864712 Hardening logic devices
03/08/2005US6864711 Programmable array logic circuit whose product and input line junctions employ single bit non-volatile ferromagnetic cells
03/08/2005US6864710 Programmable logic device
03/08/2005US6864709 Cross point switch with serializer and deserializer functions
03/08/2005US6864708 Suppressing the leakage current in an integrated circuit
03/08/2005US6864707 Universal input apparatus
03/08/2005US6864706 GTL+Driver
03/08/2005US6864704 Adjustable differential input and output drivers
03/08/2005US6864558 Layout technique for C3MOS inductive broadbanding
03/08/2005US6864539 Semiconductor integrated circuit device having body biasing circuit for generating forward well bias voltage of suitable level by using simple circuitry
03/03/2005WO2005020491A2 Programable broadcast initialization of memory blocks
03/03/2005WO2005020280A2 Method and apparatus for providing security for debug circuitry
03/03/2005WO2004105246A3 Integrated circuit arrangement, and method for programming an integrated circuit arrangement
03/03/2005US20050050479 Firmware management tool
03/03/2005US20050050412 Semiconductor circuit apparatus and test method thereof
03/03/2005US20050047511 Data receiver and data transmission system
03/03/2005US20050047247 Semiconductor integrated circuit
03/03/2005US20050047204 Ferromagnetic layer compositions and structures for spin polarized memory device
03/03/2005US20050046555 Condition monitor system responsive to different input pulses
03/03/2005US20050046473 Semiconductor integrated circuit
03/03/2005US20050046472 Data driving circuit and semiconductor memory device having the same
03/03/2005US20050046464 Step-down voltage output circuit
03/03/2005US20050046450 Pre-driver circuit and data output circuit using the same
03/03/2005US20050046449 Voltage mismatch tolerant input/output buffer
03/03/2005US20050046443 Input terminal with combined logic threshold and reset function
03/03/2005US20050046442 Input termination circuits and methods for terminating inputs
03/03/2005US20050045919 Semiconductor device
03/03/2005DE19712840B4 Schnittstellenschaltung und Verfahren zum Übertragen binärer logischer Signale mit reduzierter Verlustleistung Interface circuit and method for transmitting binary logic signals with reduced power loss
03/03/2005DE19622646B4 Integrierte Halbleiterschaltungsvorrichtung A semiconductor integrated circuit device
03/03/2005DE102004036898A1 Semiconductor integrated circuit incorporating logic gates and with protection against reverse engineering using transistors without supplementary treatment circuits
03/03/2005DE102004017262A1 Konfigurierbare Kommunikationsmodule und Verfahren zur Herstellung derselben Configurable communication modules and methods for manufacturing the same
03/02/2005EP1509826A2 Methods and apparatus for composing an identification number
03/02/2005EP1509778A1 Cell with fixed output voltage for integrated circuit
03/02/2005CN1588819A Information transmission system and method and its output signal driving device
03/02/2005CN1588802A Voltage position quasi-shift circuit
03/01/2005US6862220 Semiconductor device
03/01/2005US6861889 Amplitude converting circuit
03/01/2005US6861883 Semiconductor integrated circuit for phase management of clock domains including PLL circuit
03/01/2005US6861882 Semiconductor integrated circuit with reduced leakage current
03/01/2005US6861880 Driving circuit for push-pull operated transistors
03/01/2005US6861878 Chopper comparator
03/01/2005US6861876 Pulse evaluate logic-latch
03/01/2005US6861874 Input/output buffer
03/01/2005US6861872 Voltage down converter for low voltage operation
03/01/2005US6861871 Cascaded logic block architecture for complex programmable logic devices
03/01/2005US6861870 Dynamic cross point switch with shadow memory architecture
03/01/2005US6861869 Block symmetrization in a field programmable gate array
03/01/2005US6861868 High speed interface for a programmable interconnect circuit
03/01/2005US6861865 Apparatus and method for repairing logic blocks
03/01/2005US6861724 Semiconductor integrated circuit
02/2005
02/24/2005US20050044125 4-2 Compressor
02/24/2005US20050041513 Multi-level semiconductor memory architecture and method of forming the same
02/24/2005US20050041444 Semiconductor device
02/24/2005US20050041021 Circuit having source follower and semiconductor device having the circuit
02/24/2005US20050040889 Differential amplifier, data driver and display device
02/24/2005US20050040884 Drive circuit
02/24/2005US20050040883 Semiconductor integrated circuit device
02/24/2005US20050040881 Method of reducing leakage current in sub one volt SOI circuits
02/24/2005US20050040878 Memory device having an adjustable voltage swing setting
02/24/2005US20050040870 System toTemporarily Modify an Output Waveform
02/24/2005US20050040869 Semiconductor integrated circuit device
02/24/2005US20050040868 Reducing swing line driver
02/24/2005US20050040867 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines
02/24/2005US20050040866 Output driver comprising an improved control circuit
02/24/2005US20050040861 Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates
02/24/2005US20050040860 High speed differential pre-driver using common mode pre-charge
02/24/2005US20050040859 Logic processing apparatus, semiconductor device and logic circuit
02/24/2005US20050040858 Method and system to temporarily modify an output waveform
02/24/2005US20050040857 Methods and arrangements for enhancing domino logic
02/24/2005US20050040854 Low voltage to high voltage level shifter and related methods
02/24/2005US20050040853 High voltage to low voltage level shifter
02/24/2005US20050040852 Low voltage to extra high voltage level shifter and related methods
02/24/2005US20050040851 FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
02/24/2005US20050040850 Programmable gate array and embedded circuitry initialization and processing
02/24/2005US20050040848 Crosspoint switch with serializer and deserializer functions
02/24/2005US20050040846 Signal transmission system, and signal transmission line
02/24/2005US20050040845 Semiconductor integrated circuit device capable of controlling impedance
02/24/2005US20050040844 Apparatus and method of error detection and correction in a radiation-hardened static random access memory field- programmable gate array
02/24/2005US20050040843 Superconducting constant current source
02/24/2005US20050040804 Plate voltage generation circuit capable controlling dead band
02/24/2005DE102004036892A1 Level-down shifter for interface circuit, has circuit unit driven by power and linked to output of another circuit unit, where former unit receives output of third circuit unit
02/23/2005EP1508812A1 Scan-test method and circuit using a substitute enable signal
02/23/2005EP1296154B1 Semiconductor integrated circuit
02/23/2005CN1585271A 半导体集成电路 The semiconductor integrated circuit
02/23/2005CN1585270A Condition monitor system responsive to different input pulses
02/23/2005CN1585265A Circuit having source follower and semiconductor device having the circuit
02/23/2005CN1585112A Logic processing apparatus, semiconductor device and logic circuit
02/22/2005US6859917 Semiconductor integrated circuit having high-speed and low-power logic gates with common transistor substrate potentials, design methods thereof, and related program recording medium
02/22/2005US6859904 Apparatus and method to facilitate self-correcting memory
02/22/2005US6859423 Motor drive circuit for a disk drive apparatus
02/22/2005US6859084 Low-power voltage modulation circuit for pass devices
02/22/2005US6859075 High-speed output buffer
02/22/2005US6859074 I/O circuit using low voltage transistors which can tolerate high voltages even when power supplies are powered off
02/22/2005US6859072 Method for clock control of clocked half-rail differential logic with sense amplifier and single-rail logic
02/22/2005US6859071 Pseudofooter circuit for dynamic CMOS (Complementary metal-oxide-semiconductor) logic
02/22/2005US6859068 Self-correcting I/O interface driver scheme for memory interface
02/22/2005US6859066 Bank-based input/output buffers with multiple reference voltages
02/22/2005US6859065 Use of dangling partial lines for interfacing in a PLD
02/22/2005US6858897 Individually adjustable back-bias technique