Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
11/2005
11/10/2005WO2005107075A1 Routing architecture with high speed i/o bypass path
11/10/2005WO2005107074A2 Integrated circuit with breakdown voltage multiplier
11/10/2005WO2005107073A1 Break before make predriver and level-shifter
11/10/2005WO2004090691A3 Method and apparatus for system management using codebook correlation with symptom exclusion
11/10/2005US20050251778 System and method for dynamically executing a function in a programmable logic array
11/10/2005US20050251712 Skew adjusing circuit and semiconductor integrated circuit
11/10/2005US20050251602 Integrated circuit device that stores a value representative of an equalization co-efficient setting
11/10/2005US20050250651 Adiabatic quantum computation with superconducting qubits
11/10/2005US20050249014 Multiple electrical fuss shared with one program device
11/10/2005US20050249005 Semiconductor integrated circuit with noise reduction circuit
11/10/2005US20050248997 Semiconductor memory device for controlling output timing of data depending on frequency variation
11/10/2005US20050248925 Programmable automation controller assembly
11/10/2005US20050248892 Sub-micron high input voltage tolerant input output (I/O) circuit
11/10/2005US20050248381 Level shift circuit
11/10/2005US20050248379 Data retaining circuit
11/10/2005US20050248368 P-domino output latch with accelerated evaluate path
11/10/2005US20050248367 Digital bus synchronizer for generating read reset signal
11/10/2005US20050248366 Configurable logic and memory devices
11/10/2005US20050248365 Distributive computing subsystem of generic IC parts
11/10/2005US20050248364 Reconfiguration port for dynamic reconfiguration
11/10/2005US20050248362 Semiconductor memory device with on-die termination circuit
11/10/2005DE102005013304A1 Systeme und Verfahren zum Einstellen eines Ausgangstreibers Systems and methods for adjusting an output driver
11/10/2005DE10148338B4 Skalierbare Treibervorrichtung sowie zugehörige integrierte Schaltung Scalable device drivers and associated integrated circuit
11/09/2005EP1594274A2 Removal of a common mode voltage in a differential receiver
11/09/2005EP1594273A2 Removal of a common mode voltage in a differential receiver
11/09/2005EP1594272A2 Removal of a common mode voltage in a differential receiver
11/09/2005EP1594228A2 Architecture and interconnect scheme for programmable logic circuits
11/09/2005EP1593157A2 Integrated circuit power switch circuit sizing and placement technique
11/09/2005EP1535308A4 Protected dual-voltage microcircuit power arrangement
11/09/2005CN1695304A High speed zero DC power programmable logic device (PLD) architecture
11/09/2005CN1695303A Logic components from organic field effect transistors
11/09/2005CN1695302A A fast controlled output buffer
11/09/2005CN1694425A System, and method for extending range of a bidirectional data communication bus
11/09/2005CN1694358A Level shifter and panel display using the same
11/09/2005CN1694357A P-domino output latch with accelerated evaluate path and method for evaluating
11/09/2005CN1694356A MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop
11/09/2005CN1694351A Signal amplifier
11/09/2005CN1694327A Fuse circuit
11/09/2005CN1694253A Semiconductor memory device with on-die termination circuit
11/09/2005CN1694154A Image data transmission circuit and image data display system
11/09/2005CN1226826C Programmable buffer circuit
11/08/2005US6963237 Output circuit device for clock signal distribution in high-speed signal transmission
11/08/2005US6963231 Insulating device for a system on chip (SOC)
11/08/2005US6963228 Complementary input dynamic logic
11/08/2005US6963227 Apparatus and method for precharging and discharging a domino circuit
11/08/2005US6963225 Quad state logic design methods, circuits, and systems
11/08/2005US6963224 Reflexive optical screen, and viewing system incorporating the same
11/08/2005US6963223 Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
11/08/2005US6963222 Non-volatile product term (pterm) cell
11/08/2005US6963218 Bi-directional interface and communication link
11/08/2005US6963217 Method and apparatus for creating circuit redundancy in programmable logic devices
11/03/2005WO2005104375A1 A scalable non-blocking switching network for programmable logic
11/03/2005WO2005104374A1 Ac coupling and gate charge pumping for nmos and pmos device control
11/03/2005WO2005104369A2 Ac coupling and gate charge pumping for nmos and pmos device control
11/03/2005WO2005001724A3 Method for programming a mask-programmable logic device and device so programmed
11/03/2005US20050246598 Voltage/process evaluation in semiconductors
11/03/2005US20050246555 Transition detection at input of integrated circuit device
11/03/2005US20050246520 Reconfiguration port for dynamic reconfiguration-system monitor interface
11/03/2005US20050245226 Resistive voltage-down regulator for integrated circuit receivers
11/03/2005US20050245213 Communication apparatus
11/03/2005US20050243844 Point contact array, not circuit, and electronic circuit using the same
11/03/2005US20050243490 Semiconductor integrated circuit device and semiconductor integrated circuit system
11/03/2005US20050243201 Image data transmission circuit and image data display system
11/03/2005US20050243049 Semiconductor integrated circuit device
11/03/2005US20050242867 Differential clocking scheme in an integrated circuit having digital multiplexers
11/03/2005US20050242866 Programmable logic device having an embedded differential clock tree
11/03/2005US20050242863 Data retaining circuit
11/03/2005US20050242862 MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop
11/03/2005US20050242859 Differential master/slave CML latch
11/03/2005US20050242847 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines
11/03/2005US20050242846 Apparatus and method for handling interdevice signaling
11/03/2005US20050242842 Multi-function differential logic gate
11/03/2005US20050242841 Noise canceller circuit
11/03/2005US20050242840 Self limiting gate leakage driver
11/03/2005US20050242839 Signal amplifier
11/03/2005US20050242838 Input device for a semiconductor device
11/03/2005US20050242837 Level shifter and panel display using the same
11/03/2005US20050242836 System monitor in a programmable logic device
11/03/2005US20050242835 Reconfiguration port for dynamic reconfiguration-controller
11/03/2005US20050242834 Reconfiguration port for dynamic reconfiguration - sub-frame access for reconfiguration
11/03/2005US20050242833 On-die termination impedance calibration device
11/03/2005US20050242832 Apparatus for calibrating termination voltage of on-die termination
11/03/2005US20050242831 Tristateable cmos driver with controlled slew rate for integrated circuit i/o pads
11/03/2005US20050242830 Hybrid binary/thermometer code for controlled-voltage integrated circuit output drivers
11/03/2005US20050242829 Circuit module
11/03/2005US20050242828 High reliability memory element with improved delay time
11/03/2005US20050242669 Apparatus and method for shifting a signal from a first reference level to a second reference level
11/03/2005DE202005011866U1 Trinary half adder circuit for use in e.g. digital computer, has binary gate whose output has four different electrical potential levels that are replaced by corresponding logical numbers
11/03/2005DE202005011861U1 Tertiary full adder circuit for use in digital computer, has two tertiary half adders connected to one OR gate for producing carry over, and crossed to outputs of OR-OR and AND-AND dual gates via OR gates, respectively
11/03/2005DE102004041729A1 Integrated module for output of output signals e.g. in computing systems, uses level change minimizing function for signals being outputted
11/02/2005EP1592133A1 N-domino output latch with accelerated evaluate path
11/02/2005CN1691508A High-speed current mode logic circuit
11/02/2005CN1691507A Driver circuit
11/02/2005CN1691044A Input receiver with hysteresis and its construction method and integrated circuit
11/02/2005CN1690906A Power circuit
11/02/2005CN1225837C Output circuit
11/02/2005CN1225836C Comparison logic circuit and its compatible mode to other type of logic circuit
11/02/2005CN1225792C Substrate charge circuit for input/output electrostatic discharge protection and protection method thereof
11/01/2005US6961741 Look-up table apparatus to perform two-bit arithmetic operation including carry generation
11/01/2005US6960951 Circuit for detecting a logic transition with improved stability of the length of a detection signal pulse
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