Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
03/2005
03/24/2005US20050062503 Integrated schottky transistor logic configuration
03/24/2005US20050062502 Logic circuit whose power switch is quickly turned on and off
03/24/2005US20050062500 Self-programmable bidirectional buffer circuit and method
03/24/2005US20050062499 Bus network interface
03/24/2005US20050062498 Configurable logic element with expander structures
03/24/2005US20050062497 Field programmable gate array device
03/24/2005US20050062072 Coupled superconducting charge quantum bit device and controlled-not gate using the same
03/24/2005DE19602517B4 Flip-Flop-Steuerung Flip-flop control
03/24/2005DE10345384B3 Circuit system for computer memory arrangement has first and second circuit units connected to control device via first and second signal lines of differential signal line respectively
03/24/2005DE102004031452A1 Datenausgangstreiber Data output driver
03/23/2005EP1516363A2 Data carrier comprising an integrated circuit with an esd protection circuit
03/23/2005CN2687949Y Automatic switching control device for pulse signal
03/23/2005CN1599979A Method and system for systematic adjustments in high-speed nonstandard fet circuits
03/23/2005CN1599249A Low power dissipation CMOS type high-voltage drive circuit
03/23/2005CN1598966A Level shifter and display device using it
03/23/2005CN1194472C Logic input buffer circuit and method
03/23/2005CN1194471C Chip with even output drive buffer circuit stages and its design method
03/23/2005CN1194333C Voltage level shift unit of pure P type transistor
03/22/2005US6871311 Semiconductor integrated circuit having a self-testing function
03/22/2005US6870761 Stacked hybrid semiconductor-magnetic spin based memory
03/22/2005US6870423 Output circuit capable of transmitting signal with optimal amplitude and optimal common-mode voltage at receiver circuit
03/22/2005US6870422 Low voltage rail-to-rail CMOS input stage
03/22/2005US6870419 Memory system including a memory device having a controlled output driver characteristic
03/22/2005US6870408 Power-up circuit
03/22/2005US6870407 Thin gate oxide output drive
03/22/2005US6870400 Supply voltage detection circuit
03/22/2005US6870397 Input/output circuit with user programmable functions
03/22/2005US6870396 Tileable field-programmable gate array architecture
03/22/2005US6870395 Programmable logic devices with integrated standard-cell logic blocks
03/22/2005US6870393 Field programmable device
03/22/2005US6870391 Input buffer with CMOS driver gate current control enabling selectable PCL, GTL, or PECL compatibility
03/22/2005US6870390 Tx line driver with common mode idle state and selectable slew rates
03/22/2005US6869314 Computer connections
03/17/2005WO2005025163A1 Transmitter circuit, receiver circuit, interface circuit, and electronic device
03/17/2005WO2005025067A1 Data transfer control apparatus and electronic device
03/17/2005WO2005025066A1 Receiver circuit, interface circuit and electronic device
03/17/2005WO2004111781A3 Representing device layout using tree structure
03/17/2005US20050057986 Magnetic spin based memory with inductive write lines
03/17/2005US20050057871 Signal driving system
03/17/2005US20050057553 Scan driver and scan driving system with low input voltage, and their level shift voltage circuit
03/17/2005US20050057281 Data output driver
03/17/2005US20050057279 Input buffer of differential amplification type in semiconductor device
03/17/2005US20050057278 Push-pull output driver
03/17/2005US20050057275 Adaptive impedance output driver circuit
03/17/2005US20050057274 Tx line driver with common mode idle state and selectable slew rates
03/17/2005US20050056898 Semiconductor device
03/17/2005DE10338077A1 Tuning of drive impedance of integrated circuit chip by incrementally changing the impedance in a comparison process
03/17/2005DE102004041023A1 Semiconductor integrated circuit device, has impedance controller to generate control codes that are variably related with impedance of external reference resistor, and termination circuit to terminate transfer line based on codes
03/17/2005DE102004035273A1 Chip-Ausgangstreiber Chip output driver
03/16/2005EP1515442A1 Digitally controlled impedance for I/O of an integrated device
03/16/2005EP1514349A1 Output stage resistant against high voltage swings
03/16/2005EP1514198A2 Reconfigurable integrated circuit
03/16/2005CN1595807A Semiconductor integrated circuit in which voltage down converter output can be observed as digital value
03/16/2005CN1595796A Differential amplifier, data driver and display device
03/16/2005CN1595795A 半导体集成电路器件 The semiconductor integrated circuit device
03/16/2005CN1595533A 优先电路 Priority circuit
03/16/2005CN1193556C 信号传输装置 Signal transmitting means
03/15/2005US6868467 Information handling system including a bus in which impedance discontinuities associated with multiple expansion connectors are reduced
03/15/2005US6868029 Semiconductor device with reduced current consumption in standby state
03/15/2005US6867988 Magnetic logic elements
03/15/2005US6867637 Semiconductor integrated circuit device including a substrate bias controller and a current limiting circuit
03/15/2005US6867629 Integrated circuit and method of adjusting capacitance of a node of an integrated circuit
03/15/2005US6867620 Circuits and methods for high-capacity asynchronous pipeline
03/15/2005US6867617 Half-rate clock logic block and method for forming same
03/15/2005US6867616 Programmable logic device serial interface having dual-use phase-locked loop circuitry
03/15/2005US6867615 Dedicated input/output first in/first out module for a field programmable gate array
03/15/2005US6867574 Switch mode power supply and driving method for efficient RF amplification
03/10/2005WO2005022380A1 Data processing device
03/10/2005WO2003090229A3 Memory cells enhanced for resistance to single event upset
03/10/2005US20050055538 Dynamic logic return-to-zero latching mechanism
03/10/2005US20050055467 Methods and apparatus for breaking and resynchronizing a data link
03/10/2005US20050055395 Function block
03/10/2005US20050053161 Circuit for a transceiver output port of a local area networking device
03/10/2005US20050052936 High speed power-gating technique for integrated circuit devices incorporating a sleep mode of operation
03/10/2005US20050052800 Semiconductor integrated circuit device
03/10/2005US20050052307 Semiconductor integrated circuit in which voltage down converter output can be observed as digital value and voltage down converter output voltage is adjustable
03/10/2005US20050052219 Integrated circuit transistor body bias regulation circuit and method for low voltage applications
03/10/2005US20050052214 Level shifter circuit
03/10/2005US20050052206 Controlling signal states and leakage current during a sleep mode
03/10/2005US20050052203 Duo-mode keeper circuit
03/10/2005US20050052202 Limited switch dynamic logic circuit with keeper
03/10/2005US20050052200 Calibration methods and circuits for optimized on-die termination
03/10/2005US20050051802 Semiconductor device
03/09/2005EP1513256A1 Output buffer with independently controllable current mirror legs
03/09/2005EP1512223A2 Programmable logic device having heterogeneous programmable logic blocks
03/09/2005EP1344071B1 Asynchronous reset circuit testing
03/09/2005CN1592284A Data receiver and data transmission system
03/09/2005CN1592111A Bus level converting system for liquid crystal TV set
03/09/2005CN1592109A 半导体装置 Semiconductor device
03/09/2005CN1592054A Step-down voltage output circuit
03/09/2005CN1591683A 数据输出驱动器 Data output drivers
03/08/2005US6865705 Semiconductor integrated circuit device capable of switching mode for trimming internal circuitry through JTAG boundary scan method
03/08/2005US6865703 Scan test system for semiconductor device
03/08/2005US6864731 Method and device for symmetrical slew rate calibration
03/08/2005US6864725 Low current wide VREF range input buffer
03/08/2005US6864720 Semiconductor integrated circuit and circuit designating system
03/08/2005US6864719 Semiconductor device protecting built-in transistor from the voltage applied at test mode
03/08/2005US6864716 Reconfigurable memory architecture
03/08/2005US6864715 Windowing circuit for aligning data and clock signals
03/08/2005US6864714 PLDs providing reduced delays in cascade chain circuits
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