Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2013
12/18/2013CN103456784A High-voltage P-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method
12/18/2013CN103456783A High-breakdown-voltage P-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method
12/18/2013CN103456782A Semiconductor device and production method thereof
12/18/2013CN103456781A Compound semiconductor transistor with self aligned gate
12/18/2013CN103456780A Epitaxy improved structure of pseudo crystal high electronic mobility transistor and heterojunction bipolar transistor and processing method thereof
12/18/2013CN103456777A Heterojunction bipolar transistor structure with high current gain and processing method thereof
12/18/2013CN103456775A Metal gate electrode of a semiconductor device
12/18/2013CN103456774A Semiconductor device having non-orthogonal element
12/18/2013CN103456773A Schottky diode and production method thereof
12/18/2013CN103456772A Semiconductor device and method for manufacturing the same
12/18/2013CN103456771A Structure for achieving control of service life of carrier in semiconductor device and manufacturing method thereof
12/18/2013CN103456770A Semiconductor device having embedded strain-inducing pattern and method of forming the same
12/18/2013CN103456769A Semiconductor Device with Trench Structures
12/18/2013CN103456768A Semiconductor isolation structure with air gaps in deep trenches
12/18/2013CN103456767A Mos structure and manufacturing method thereof
12/18/2013CN103456766A Organic light emitting diode (OLED) panel thinning device, system and method
12/18/2013CN103456760A Organic light emitting display device and method of manufacturing the same
12/18/2013CN103456756A Active pixel structure and manufacture method thereof
12/18/2013CN103456752A Cmos image sensor and method for forming the same
12/18/2013CN103456747A Array substrate, manufacturing method of array substrate and display device
12/18/2013CN103456746A Array substrate, manufacturing method thereof and display device
12/18/2013CN103456745A Array substrate, manufacturing method thereof and display device
12/18/2013CN103456744A Array substrate, preparing method of array substrate and display device
12/18/2013CN103456743A Array substrate, manufacturing method of array substrate, flexible display device and electronic device
12/18/2013CN103456742A Array substrate, manufacturing method of array substrate and display device
12/18/2013CN103456741A Array substrate, manufacturing method of array substrate and display device
12/18/2013CN103456740A Pixel unit and manufacturing method thereof, array substrate and display device
12/18/2013CN103456739A Array substrate, manufacturing method thereof and display device
12/18/2013CN103456737A Semiconductor device and method of manufacturing the same
12/18/2013CN103456736A Semiconductor device and method of forming the same
12/18/2013CN103456735A Cmos device and manufacturing method thereof
12/18/2013CN103456734A Asymmetric LDMOS process deviation monitoring structure and manufacturing method thereof
12/18/2013CN103456731A Low voltage protection devices for precision transceivers and methods of forming the same
12/18/2013CN103456723A Ferroelectric crystal film, electronic component, manufacturing method of ferroelectric crystal film, and manufacturing apparatus therefor
12/18/2013CN103456717A Measurement structure and method for resistance of active region and polysilicon bevels on semiconductor device
12/18/2013CN103456716A Three-dimensional multi-chip stacking module and manufacturing method thereof
12/18/2013CN103456715A Intermediary base material and manufacturing method thereof
12/18/2013CN103456714A Semiconductor device and method of manufacturing thereof
12/18/2013CN103456711A Fin-type anti-fuse structure and manufacturing method thereof
12/18/2013CN103456710A Mos device and manufacturing method thereof
12/18/2013CN103456708A Devices and methods for improved reflective electron beam lithography
12/18/2013CN103456707A Semiconductor packaging structure and manufacturing method
12/18/2013CN103456706A Discrete semiconductor device package and manufacturing method
12/18/2013CN103456704A Design scheme for connector site spacing and resulting structures
12/18/2013CN103456703A Semiconductor package and fabrication method thereof
12/18/2013CN103456701A Integrated circuit die assembly with heat spreader
12/18/2013CN103456699A Integrated circuit packaging structure and packaging method thereof
12/18/2013CN103456698A Chip package structure and chip packaging method
12/18/2013CN103456697A Isolation rings for packages and the method of forming the same
12/18/2013CN103456696A Package substrate and method of manufacturing the same
12/18/2013CN103456694A Semiconductor device with air gap and method for fabricating the same
12/18/2013CN103456693A Middle in-situ doped sige junctions for pmos devices
12/18/2013CN103456692A Method for forming complementary metal-oxide-semiconductor tube
12/18/2013CN103456691A CMOS (complementary metal oxide semiconductor) manufacturing method
12/18/2013CN103456690A Semiconductor device and manufacturing method of semiconductor device
12/18/2013CN103456689A Device for separating flexible substrate from glass substrate and production device
12/18/2013CN103456688A Interposer die for semiconductor packaging
12/18/2013CN103456687A Array substrate and manufacturing method thereof
12/18/2013CN103456686A Method of manufacturing semiconductor device
12/18/2013CN103456685A Manufacturing method for TSV and first layer re-wiring layer needless of using CMP
12/18/2013CN103456684A Manufacturing method of temperature safety valve (TSV) back connection end
12/18/2013CN103456683A Methods of forming a through via structure, image sensor and integrated circuit
12/18/2013CN103456682A Semiconductor processing method and semiconductor structure
12/18/2013CN103456681A Method and apparatus for back end of line semiconductor device processing
12/18/2013CN103456680A Method for forming holes and grooves in low K medium layer
12/18/2013CN103456679A Interconnection structure and manufacturing method thereof
12/18/2013CN103456678A Barrier stack structure and method for forming same
12/18/2013CN103456677A Semiconductor device and manufacturing method thereof
12/18/2013CN103456676A Contact silicon recess etching method
12/18/2013CN103456675A Shallow trench isolation structure manufacturing method and semiconductor device
12/18/2013CN103456674A Method for preparing deep groove morphology analyzing sample
12/18/2013CN103456673A STI (shallow trench isolation) preparation method and CMOS (complementary metal oxide semiconductor) manufacturing method
12/18/2013CN103456672A Open type supporting board for pin
12/18/2013CN103456671A Wafer table and photoetching system
12/18/2013CN103456670A Method of switching wafers in photoetching device
12/18/2013CN103456669A Thin substrate electrostatic chuck system and method
12/18/2013CN103456668A Method and device for peeling off silicon wafers
12/18/2013CN103456667A Attaching bench
12/18/2013CN103456666A Wafer cleaning device with a plurality of groups of bayonets and wafer cleaning method
12/18/2013CN103456665A Substrate treating apparatus and substrate treating method
12/18/2013CN103456664A Apparatus and method for drying substrate
12/18/2013CN103456663A Substrate treating apparatus and substrate treating method
12/18/2013CN103456662A Substrate separation device and method for separating the substrate using thereof
12/18/2013CN103456661A UV curing system for semiconductors
12/18/2013CN103456660A Plasma reinforcement cleaning device and system and method for cleaning wafers
12/18/2013CN103456659A Method for manufacturing photoetching registration mark for manufacturing semiconductor device
12/18/2013CN103456658A Detection method of semiconductor blind holes
12/18/2013CN103456657A Detection method of blind holes
12/18/2013CN103456656A Detection method of semiconductor blind holes
12/18/2013CN103456655A Detection method of semiconductor blind holes
12/18/2013CN103456654A Measurement method
12/18/2013CN103456653A Detection method of semiconductor blind holes
12/18/2013CN103456652A Mixed bonding implementation method
12/18/2013CN103456651A Slice bonding working table
12/18/2013CN103456650A Eyepoint training method for wire bond and related semiconductor processing operation
12/18/2013CN103456649A Method for encapsulating semiconductors
12/18/2013CN103456648A Protecting method of diode/transistor wafer PN junction
12/18/2013CN103456647A Integrated circuit packaging system with substrate and method of manufacture thereof
12/18/2013CN103456646A Method for preparing multilayer low-temperature cofired ceramics integrated liquid cooling circulation channel
12/18/2013CN103456645A Packaging-after etching three-dimensional system-on-chip upright stacking packaging structure and technology method