Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2005
05/12/2005WO2004079780A3 A method of patterning photoresist on a wafer using a reflective mask with a multi-layer arc
05/12/2005WO2004077548A3 Connection technology for power semiconductors
05/12/2005WO2004053979A8 A method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
05/12/2005WO2004042780A3 Flexible semiconductor device and method of manufacturing the same
05/12/2005WO2003081666A8 Production method for a contact in a semiconductor structure and corresponding contact
05/12/2005US20050102723 Method of operating a lithographic processing machine, control system, lithographic apparatus, lithographic processing cell, and computer program
05/12/2005US20050102720 Magnetic tunnel junction device with etch stop layer and dual-damascene conductor
05/12/2005US20050102648 Orientation dependent shielding for use with dipole illumination techniques
05/12/2005US20050102647 Method and program for supporting register-transfer-level design of semiconductor integrated circuit
05/12/2005US20050102591 Failure detection system, failure detection method, and computer program product
05/12/2005US20050102446 Semiconductor integrated circuit device
05/12/2005US20050102426 Methods, systems and computer program products for developing resource monitoring systems from observational data
05/12/2005US20050102263 Exposure apparatus and device manufacturing method
05/12/2005US20050102108 Tailored temperature uniformity
05/12/2005US20050102064 Method and apparatus for self-calibration of a substrate handling robot
05/12/2005US20050101686 UV curable composition for forming dielectric coatings and related method
05/12/2005US20050101685 UV curable composition for forming dielectric coatings and related method
05/12/2005US20050101500 Resist remover composition
05/12/2005US20050101282 Semiconductor integrated circuit
05/12/2005US20050101160 Silicon thin film transistors and solar cells on plastic substrates
05/12/2005US20050101159 High K dielectric film
05/12/2005US20050101157 Method for manufacturing semiconductor device
05/12/2005US20050101156 Film forming apparatus and film forming method
05/12/2005US20050101155 Ramp temperature techniques for improved mean wafer before clean
05/12/2005US20050101154 Plasma treatment to enhance adhesion and to minimize oxidation of carbon-containing layers
05/12/2005US20050101153 Method for producing multicrystalline silicon substrate for solar cells
05/12/2005US20050101152 Method of manufacturing flotox type eeprom
05/12/2005US20050101150 Methods of enhancing selectivity of etching silicon dioxide relative to one or more organic substances; and plasma reaction chambers
05/12/2005US20050101149 Dry etching method and apparatus for use in the LCD device
05/12/2005US20050101148 Method for preventing an increase in contact hole width during contact formation
05/12/2005US20050101147 Method for integrating a high-k gate dielectric in a transistor fabrication process
05/12/2005US20050101146 Method for forming bond pad openings
05/12/2005US20050101145 Semiconductor structure and method of fabrication
05/12/2005US20050101144 Method and apparatus for treating a substrate surface by bubbling
05/12/2005US20050101143 Methods of fabricating a semiconductor device and forming a trench region in a semiconductor device
05/12/2005US20050101142 Ferroelectric capacitor devices and a method for compensating for damage to a capacitor caused by etching
05/12/2005US20050101141 Method of forming conductive stud on vertical memory device
05/12/2005US20050101140 Method of plasma etching
05/12/2005US20050101138 System and method for applying constant pressure during electroplating and electropolishing
05/12/2005US20050101137 Plasma etching method
05/12/2005US20050101136 Etching method and method of manufacturing circuit device using the same
05/12/2005US20050101135 Minimizing the loss of barrier materials during photoresist stripping
05/12/2005US20050101134 Method for etching a thin metal layer
05/12/2005US20050101133 Method for making negative thermal expansion material zirconium tungstate
05/12/2005US20050101132 Copper interconnect structure having stuffed diffusion barrier
05/12/2005US20050101131 Devices containing zirconium-platinum-containing materials and methods for preparing such materials and devices
05/12/2005US20050101130 Method and tool of chemical doping CoW alloys with Re for increasing barrier properties of electroless capping layers for IC Cu interconnects
05/12/2005US20050101129 Methods of forming via plugs using an aerosol stream of particles to deposit conductive material
05/12/2005US20050101128 Method of patterning damascene structure in integrated circuit design
05/12/2005US20050101127 Method of manufacturing semiconductor device that includes forming self-aligned contact pad
05/12/2005US20050101126 Line edge roughness reduction for trench etch
05/12/2005US20050101125 Damage-free resist removal process for ultra-low-k processing
05/12/2005US20050101124 Via contact forming method
05/12/2005US20050101123 Via-filling material and process for fabricating semiconductor integrated circuit using the material
05/12/2005US20050101122 Method for fabricating semiconductor device
05/12/2005US20050101121 Method of forming metal line in semiconductor device
05/12/2005US20050101120 Method of forming local interconnect barrier layers
05/12/2005US20050101119 Insulating layer having graded densification
05/12/2005US20050101118 Semiconductor device and method of manufacturing the same
05/12/2005US20050101117 Semiconductor device with multi-layered wiring arrangement including reinforcing patterns, and production method for manufacturing such semiconductor device
05/12/2005US20050101116 Integrated circuit device and the manufacturing method thereof
05/12/2005US20050101115 Formation method of SiGe HBT
05/12/2005US20050101113 Method for making a semiconductor device having a metal gate electrode
05/12/2005US20050101112 Methods of nanotubes films and articles
05/12/2005US20050101111 SOI chip with mesa isolation and recess resistant regions
05/12/2005US20050101110 Novel method to reduce the fluorine contamination on the Al/Al-Cu pad by a post high cathod temperature plasma treatment
05/12/2005US20050101109 Controlled fracture substrate singulation
05/12/2005US20050101108 Semiconductor wafer dividing method
05/12/2005US20050101107 Method for manufacturing semiconductor device
05/12/2005US20050101106 Method of manufacturing a semiconductor device
05/12/2005US20050101105 Methods for fabricating final substrates
05/12/2005US20050101104 Process for detaching layers of material
05/12/2005US20050101103 Method and apparatus for joining adhesive tape to back face of semiconductor wafer
05/12/2005US20050101102 Non-volatile memory and manufacturing method using STI trench implantation
05/12/2005US20050101101 Forming a trench to define one or more isolation regions in a semiconductor structure
05/12/2005US20050101100 Integrated devices with optical and electrical isolation and method for making
05/12/2005US20050101099 Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode
05/12/2005US20050101098 Method of forming a varactor
05/12/2005US20050101097 Semiconductor device and process of producing the same
05/12/2005US20050101096 Self-aligned lateral heterojunction bipolar transistor
05/12/2005US20050101095 Method for producing a stacked structure
05/12/2005US20050101094 Semiconductor device having trench capacitor and fabrication method for the same
05/12/2005US20050101093 Method for preventing to form a spacer undercut in seg pre-clean process
05/12/2005US20050101092 Methods of fabricating semiconductor devices
05/12/2005US20050101091 Semiconductor device having a trench isolation and method of fabricating the same
05/12/2005US20050101090 Floating gate and fabrication method therefor
05/12/2005US20050101089 Method of manufacturing a flash memory cell using a self-aligned floating gate
05/12/2005US20050101088 Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells
05/12/2005US20050101087 Semiconductor memory device and its production process
05/12/2005US20050101086 Conductive memory stack with non-uniform width
05/12/2005US20050101085 Semiconductor device and method for fabricating the same
05/12/2005US20050101083 Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing
05/12/2005US20050101082 Composite material, wafer holding member and method for manufacturing the same
05/12/2005US20050101081 Nonvolatile semiconductor memory and a fabrication method thereof
05/12/2005US20050101080 Non-volatile memory device and method of forming
05/12/2005US20050101078 Capacitor constructions
05/12/2005US20050101077 Sacrificial shallow trench isolation oxide liner for strained-silicon channel CMOS devices
05/12/2005US20050101076 Memory embedded semiconductor device and method for fabricating the same
05/12/2005US20050101075 Method of forming a field effect transistors
05/12/2005US20050101074 Semiconductor device and method of manufacturing the same
1 ... 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 ... 6590