Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2005
05/19/2005WO2005045907A1 Method for making semiconductor integrated circuit device
05/19/2005WO2005045906A1 System and method for electroless surface conditioning
05/19/2005WO2005045905A1 Tailored temperature uniformity
05/19/2005WO2005045904A2 Notch-free etching of high aspect soi structures using a time division multiplex process and rf bias modulation
05/19/2005WO2005045903A2 Method for making a flat-top pad
05/19/2005WO2005045902A2 Semiconductor device and manufacturing method thereof
05/19/2005WO2005045901A2 METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES
05/19/2005WO2005045900A2 Method of fabricating a finfet
05/19/2005WO2005045899A2 Low temperature deposition of silicone nitride
05/19/2005WO2005045895A2 Cleaning solutions and etchants and methods for using same
05/19/2005WO2005045892A2 Confined spacers for double gate transistor semiconductor fabrication process
05/19/2005WO2005045887A2 Method of forming an nmos transistor and structure thereof
05/19/2005WO2005045886A2 Automated material handling system
05/19/2005WO2005045885A2 Anti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems
05/19/2005WO2005045509A2 Electro-optic displays
05/19/2005WO2005044969A1 Solvent compositions containing chlorofluoroolefins or hydrochiloroolefins
05/19/2005WO2005044899A1 Prepolymer, prepolymer composition, high molecular weight polymer having structure containing hole and electrically insulating film
05/19/2005WO2005044695A1 Low cost wafer box improvements
05/19/2005WO2005044474A1 Scrubber box and method for using the same
05/19/2005WO2005044451A1 Electrical connection of components
05/19/2005WO2005034209A3 Thin buried oxides by low-dose oxygen implantation into modified silicon
05/19/2005WO2005028994A3 System and method for integrated multi-use optical alignment
05/19/2005WO2005027194A3 Method of making nonvolatile transistor pairs with shared control gate
05/19/2005WO2005017975A3 Anchors for microelectromechanical systems having an soi substrate, and method of fabricating same
05/19/2005WO2005013318B1 Method for obtaining a thin high-quality layer by co-implantation and thermal annealing
05/19/2005WO2005013281A3 Nonvolatile memory and method of making same
05/19/2005WO2005010933A3 Micromirrors with mechanisms for enhancing coupling of the micromirrors with electrostatic fields
05/19/2005WO2005006424A8 Method and apparatus for removing a residual organic layer from a substrate using reactive gases
05/19/2005WO2005001593A3 Reference pattern extraction method and device, pattern matching method and device, position detection method and device, and exposure method and device
05/19/2005WO2004109776A3 SiGe LATTICE ENGINEERING USING A COMBINATION OF OXIDATION THINNING AND EPITAXIAL REGROWTH
05/19/2005WO2004102620B1 Method to passivate conductive surfaces during semiconductor processing
05/19/2005WO2004095526A3 Multi-bit non-volatile memory device and method therefor
05/19/2005WO2004093084A3 Mram architecture and a method and system for fabricating mram memories utilizing the architecture
05/19/2005WO2004086845A3 Flip-chip assembley with thin underfill and thick solder mask
05/19/2005WO2004077547A3 Internal connection system for power semiconductors comprising large-area terminals
05/19/2005WO2004077546A3 Self-supporting contacting structures that are directly produced on components without housings
05/19/2005WO2004061952A3 Method of forming a multi-layer semiconductor structure having a seamless bonding interface
05/19/2005WO2004061932A9 Method and apparatus for planarization of a material by growing a sacrificial film with customized thickness profile
05/19/2005WO2004053928A3 Methods of measuring integrated circuit structure and preparation thereof
05/19/2005WO2004030039A3 Apparatus and method of using thin film material as diffusion barrier for metallization
05/19/2005WO2004025724A9 Jet singulation of a substrate
05/19/2005WO2003083933A8 Treating device for element to be treated and treating method
05/19/2005US20050108676 Method for fabricating a liquid crystal display
05/19/2005US20050108673 CAD method for arranging via-holes, a CAD tool, photomasks produced by the CAD method, a semiconductor integrated circuit manufactured with photomasks and a computer program product for executing the CAD method
05/19/2005US20050108668 Device and method for floorplanning semiconductor integrated circuit
05/19/2005US20050108606 Input/output switching arrangement for semiconductor circuits, a method for testing driver circuits in semiconductor circuits
05/19/2005US20050108603 Input switching arrangement for a semiconductor circuit and test method for unidirectional input drivers in semiconductor circuits
05/19/2005US20050108577 Remote diagnostic system for facilities and remote diagnostic method
05/19/2005US20050108459 Integrated memory circuit
05/19/2005US20050107971 Apparatus and method for processing a microelectronic workpiece using metrology
05/19/2005US20050107904 Semiconductor manufacturing line availability evaluating system and design system
05/19/2005US20050107575 Unsaturated ester substituted polymers with reduced halogen content
05/19/2005US20050107542 Film adhesives containing maleimide compounds and methods for use thereof
05/19/2005US20050107283 Volatile copper (II) complexes and reducing agents for deposition of copper films by atomic layer deposition
05/19/2005US20050107274 diketone compound is preferably selected from the group consisting of: acetonylacetone, acetylacetone, trifluoroacetylacetone, hexafluoroacetylacetone, thienoyltrifluoroacetylacetone, and 2,2-dimethyl-6,6,7,7,8,8,8-heptafluoro-3,5-octanedione
05/19/2005US20050107242 Zeolite-carbon doped oxide composite low k dielectric
05/19/2005US20050107012 Method and apparatus for polishing a substrate while washing a polishing pad of the apparatus with at least one free-flowing vertical stream of liquid
05/19/2005US20050107010 Planarizing solutions, planarizing machines and methods for mechanical or chemical-mechanical planarization of microelectronic-device substrate assemblies
05/19/2005US20050107009 Polishing pad having slurry utilization enhancing grooves
05/19/2005US20050106919 Contact for use in an integrated circuit and a method of manufacture therefor
05/19/2005US20050106898 Silicon nitride film and semiconductor device, and manufacturing method thereof
05/19/2005US20050106897 Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method
05/19/2005US20050106896 Processing apparatus and method
05/19/2005US20050106895 Supercritical water application for oxide formation
05/19/2005US20050106894 Semiconductor device and method for fabricating same
05/19/2005US20050106893 Surface preparation prior to deposition on germanium
05/19/2005US20050106892 Etching method
05/19/2005US20050106891 Conditioning of a reaction chamber
05/19/2005US20050106890 Method for forming a trench in a layer or a layer stack on a semiconductor wafer
05/19/2005US20050106889 Method of preventing photoresist residues
05/19/2005US20050106888 Method of in-situ damage removal - post O2 dry process
05/19/2005US20050106887 Method for formimg contact holes
05/19/2005US20050106886 Method to modulate etch rate in SLAM
05/19/2005US20050106885 Multi-layer interconnect with isolation layer
05/19/2005US20050106884 Silicon carbide components of semiconductor substrate processing apparatuses treated to remove free-carbon
05/19/2005US20050106883 Crystal manufacturing method
05/19/2005US20050106882 Dynamically controllable reduction of vertical contact diameter through adjustment of etch mask stack for dielectric etch
05/19/2005US20050106881 Wafer reuse techniques
05/19/2005US20050106880 Chemical mechanical planarization pad
05/19/2005US20050106879 Method for thinning wafers that have contact bumps
05/19/2005US20050106878 Polishing pad having a groove arrangement for reducing slurry consumption
05/19/2005US20050106877 Method for depositing nanolaminate thin films on sensitive surfaces
05/19/2005US20050106876 Apparatus and method for real time measurement of substrate temperatures for use in semiconductor growth and wafer processing
05/19/2005US20050106875 Plasma ashing method
05/19/2005US20050106874 Method of manufacturing a semiconductor device
05/19/2005US20050106873 Plasma chamber having multiple RF source frequencies
05/19/2005US20050106872 Copper CMP defect reduction by extra slurry polish
05/19/2005US20050106871 Method of simultaneously fabricating isolation structures having rounded and unrounded corners
05/19/2005US20050106870 Methods for using a silylation technique to reduce cell pitch in semiconductor devices
05/19/2005US20050106869 Plasma processing apparatus
05/19/2005US20050106868 Etching method
05/19/2005US20050106866 Method of manufacturing semiconductor device
05/19/2005US20050106865 Integration of ALD tantalum nitride for copper metallization
05/19/2005US20050106864 Process and device for depositing semiconductor layers
05/19/2005US20050106863 Semiconductor wafer manufacturing methods employing cleaning delay period
05/19/2005US20050106862 Method for forming low-k dielectric layer of semiconductor device
05/19/2005US20050106861 Resistless lithography method for fabricating fine structures
05/19/2005US20050106860 [method of fabricating a contact]
05/19/2005US20050106859 Methods of forming silicide films with metal films in semiconductor devices and contacts including the same
05/19/2005US20050106858 Method and system for fabricating a copper barrier layer with low dielectric constant and leakage current
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