Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2005
05/17/2005US6894295 Emission collimation beams; masking patterns
05/17/2005US6894294 Reducing impurities; using electron beams; integrated circuit milling
05/17/2005US6894293 System for recycling gases used in a lithography tool
05/17/2005US6894291 Apparatus and methods for blocking highly scattered charged particles in a patterned beam in a charged-particle-beam microlithography system
05/17/2005US6894277 Scanning electron microscope
05/17/2005US6894261 Position measuring system for use in lithographic apparatus
05/17/2005US6894245 Radio frequency plasma; magnetic generator; for semiconductor
05/17/2005US6894104 A curable protective coatings material for protecting contactor or holes during etching silicon wafer
05/17/2005US6893988 Method for manufacturing non-volatile memory
05/17/2005US6893987 Simple process for fabricating semiconductor devices
05/17/2005US6893986 Method of reducing internal stress in materials
05/17/2005US6893985 UV-activated dielectric layer
05/17/2005US6893984 Evaporated LaA1O3 films for gate dielectrics
05/17/2005US6893983 Method for depositing a very high phosphorus doped silicon oxide film
05/17/2005US6893982 Method for forming a thin film, methods for forming a gate electrode and transistor using the same, and a gate electrode manufactured using the same
05/17/2005US6893981 Method of manufacturing a semiconductor device by RTA process in nitrogen atmosphere
05/17/2005US6893980 Semiconductor device and manufacturing method therefor
05/17/2005US6893979 Method for improved plasma nitridation of ultra thin gate dielectrics
05/17/2005US6893978 Method for oxidizing a metal layer
05/17/2005US6893977 Method of manufacturing a semiconductor device
05/17/2005US6893975 System and method for etching a mask
05/17/2005US6893974 System and method for fabricating openings in a semiconductor topography
05/17/2005US6893973 Method of etching silicon nitride film and method of producing semiconductor device
05/17/2005US6893972 Applying a resist film to a substrate, producing a resist structure with webs having sidewall structures chemically amplified in a dry etching resistance and removing unamplified sections
05/17/2005US6893971 Dry etching method and apparatus
05/17/2005US6893970 Plasma processing method
05/17/2005US6893969 Use of ammonia for etching organic low-k dielectrics
05/17/2005US6893968 Defect-minimizing, topology-independent planarization of process surfaces in semiconductor devices
05/17/2005US6893965 Method of producing semiconductor device
05/17/2005US6893964 Cleaning method for substrate treatment device and substrate treatment device
05/17/2005US6893963 Method for forming a titanium nitride layer
05/17/2005US6893962 Low via resistance system
05/17/2005US6893961 Methods for making metallization structures for semiconductor device interconnects
05/17/2005US6893960 Method for manufacturing a semiconductor device
05/17/2005US6893959 Method to form selective cap layers on metal features with narrow spaces
05/17/2005US6893958 Methods for preventing cross-linking between multiple resists and patterning multiple resists
05/17/2005US6893957 Method of forming a dual damascene interconnect by selective metal deposition
05/17/2005US6893956 Barrier layer for a copper metallization layer including a low-k dielectric
05/17/2005US6893954 Method for patterning a semiconductor wafer
05/17/2005US6893953 Fabrication process of a semiconductor device including a CVD process of a metal film
05/17/2005US6893952 Methods of forming a ball grid array including a non-conductive polymer core and a silver or silver alloy outer layer
05/17/2005US6893950 Contact structure for an electrically operated II/VI semiconductor element and process for the production thereof
05/17/2005US6893949 Semiconductor devices having contact plugs and local interconnects and methods for making the same
05/17/2005US6893948 Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size
05/17/2005US6893947 Advanced RF enhancement-mode FETs with improved gate properties
05/17/2005US6893946 Method for manufacturing semiconductor thin film, and magnetoelectric conversion element provided with semiconductor thin film thereby manufactured
05/17/2005US6893945 Method for manufacturing gallium nitride group compound semiconductor
05/17/2005US6893944 Method of manufacturing a semiconductor wafer
05/17/2005US6893943 Method of dividing a semiconductor wafer
05/17/2005US6893942 Method for separating a mask from the surface of a semiconductor wafer
05/17/2005US6893940 Method of manufacturing semiconductor device
05/17/2005US6893939 Thermal physical vapor deposition source with minimized internal condensation effects
05/17/2005US6893938 STI formation for vertical and planar transistors
05/17/2005US6893937 Method for preventing borderless contact to well leakage
05/17/2005US6893936 Method of Forming strained SI/SIGE on insulator with silicon germanium buffer
05/17/2005US6893935 Semiconductor component and fabrication method
05/17/2005US6893934 Bipolar transistor device having phosphorous
05/17/2005US6893933 Bipolar transistors with low-resistance emitter contacts
05/17/2005US6893932 Heterojunction bipolar transistor containing at least one silicon carbide layer
05/17/2005US6893931 Reducing extrinsic base resistance in an NPN transistor
05/17/2005US6893930 Fabrication of field effect transistor with shallow junctions using low temperature activation of antimony
05/17/2005US6893929 Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends
05/17/2005US6893928 Semiconductor device and method of manufacturing the same
05/17/2005US6893927 Method for making a semiconductor device with a metal gate electrode
05/17/2005US6893924 Dual metal-alloy nitride gate electrodes
05/17/2005US6893923 Reduced mask count process for manufacture of mosgated device
05/17/2005US6893922 Non-volatile memory device and manufacturing method thereof
05/17/2005US6893921 Nonvolatile memories with a floating gate having an upward protrusion
05/17/2005US6893920 Method for forming a protective buffer layer for high temperature oxide processing
05/17/2005US6893919 Floating gate and fabricating method of the same
05/17/2005US6893918 Method of fabricating a flash memory
05/17/2005US6893917 Structure and fabricating method to make a cell with multi-self-alignment in split gate flash
05/17/2005US6893916 Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same
05/17/2005US6893915 Semiconductor device having barrier layer between ruthenium layer and metal layer and method for manufacturing the same
05/17/2005US6893914 Method for manufacturing semiconductor device
05/17/2005US6893913 Method for forming capacitor of semiconductor device
05/17/2005US6893912 Ferroelectric capacitor memory device fabrication method
05/17/2005US6893911 Process integration for integrated circuits
05/17/2005US6893910 One step deposition method for high-k dielectric and metal gate electrode
05/17/2005US6893909 Method of manufacturing metal-oxide-semiconductor transistor
05/17/2005US6893908 Thin film transfer array substrate for liquid crystal display and method for fabricating same
05/17/2005US6893906 Electro-optical device and driving method for the same
05/17/2005US6893905 Method of forming substantially hillock-free aluminum-containing components
05/17/2005US6893904 Stereolithographic methods of fabricating semiconductor devices having protective layers thereon through which contact pads are exposed
05/17/2005US6893903 Semiconductor device and method for manufacturing the same
05/17/2005US6893901 Carrier with metal bumps for semiconductor die packages
05/17/2005US6893900 Method of making an integrated circuit package
05/17/2005US6893898 Semiconductor device and a method of manufacturing the same
05/17/2005US6893896 Method for making multilayer thin-film electronics
05/17/2005US6893894 Method of manufacturing a compound semiconductor by heating a layered structure including rare earth transition metal
05/17/2005US6893893 Method of preventing short circuits in magnetic film stacks
05/17/2005US6893892 Porous gas sensors and method of preparation thereof
05/17/2005US6893891 Process for fabricating a semiconductor diffraction grating using a sacrificial layer
05/17/2005US6893885 Method for electrically and mechanically connecting microstructures using solder
05/17/2005US6893882 Multivariate RBR tool aging detector
05/17/2005US6893805 Substrate processing apparatus and substrate processing method
05/17/2005US6893801 Fabrication method of semiconductor integrated circuit device
05/17/2005US6893800 Substrate topography compensation at mask design: 3D OPC topography anchored
05/17/2005US6893799 Dual-solder flip-chip solder bump
05/17/2005US6893794 Chemical amplification type positive resist composition
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