Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2006
06/13/2006US7061015 Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion
06/13/2006US7061014 Natural-superlattice homologous single crystal thin film, method for preparation thereof, and device using said single crystal thin film
06/13/2006US7061008 Single molecule array on silicon substrate for quantum computer
06/13/2006US7061006 Light emission from semiconductor integrated circuits
06/13/2006US7060996 Mask, method of producing mask, and method of producing semiconductor device
06/13/2006US7060994 Exposure apparatus and method
06/13/2006US7060993 Device, EUV-lithographic device and method for preventing and cleaning contamination on optical elements
06/13/2006US7060990 Stage base, substrate processing apparatus, and maintenance method for stage
06/13/2006US7060985 Multipole field-producing apparatus in charged-particle optical system and aberration corrector
06/13/2006US7060984 Multi-charged beam lens and charged beam exposure apparatus using the same
06/13/2006US7060960 Solid-state imaging device and method of manufacturing the same
06/13/2006US7060945 Substrate heater and fabrication method for the same
06/13/2006US7060944 Heat treatment device and heat treatment method
06/13/2006US7060939 Substrate heating method, substrate heating system, and applying developing system
06/13/2006US7060931 Neutral beam source having electromagnet used for etching semiconductor device
06/13/2006US7060909 Composition for forming low dielectric constant insulating film, method of forming insulating film using the composition and electronic parts having the insulating film produced thereby
06/13/2006US7060786 Heat resistant resin composition and adhesive film
06/13/2006US7060638 Method of forming low dielectric constant porous films
06/13/2006US7060637 Methods of forming intermediate semiconductor device structures using spin-on, photopatternable, interlayer dielectric materials
06/13/2006US7060636 Tunable dielectric device and process relating thereto
06/13/2006US7060635 Method of manufacturing semiconductor device and method of forming pattern
06/13/2006US7060634 Materials and methods for forming hybrid organic-inorganic dielectric materials for integrated circuit applications
06/13/2006US7060633 Planarization for integrated circuits
06/13/2006US7060632 Methods for fabricating strained layers on semiconductor substrates
06/13/2006US7060631 exposing a base surface with exposed copper of a substrate having an opening extending through 2 layers of insulation to a cleaning solution formed from hydrochloric acid, nitric acid and hydrofluoric acid; less than 5 Angstroms of the insulation from sidewalls of the opening are removed
06/13/2006US7060630 Method of forming isolation film of semiconductor device
06/13/2006US7060629 Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device
06/13/2006US7060628 Method for fabricating a hard mask polysilicon gate
06/13/2006US7060627 Method of decreasing charging effects in oxide-nitride-oxide (ONO) memory arrays
06/13/2006US7060626 Multi-run selective pattern and etch wafer process
06/13/2006US7060625 Imprint stamp
06/13/2006US7060624 Deep filled vias
06/13/2006US7060623 Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern
06/13/2006US7060622 Method of forming dummy wafer
06/13/2006US7060621 Slurry for CMP, polishing method and method of manufacturing semiconductor device
06/13/2006US7060620 Method of preparing a surface of a semiconductor wafer to make it epiready
06/13/2006US7060619 Reduction of the shear stress in copper via's in organic interlayer dielectric material
06/13/2006US7060618 Semiconductor device, method for manufacturing the same, and plating solution
06/13/2006US7060617 Method of protecting a seed layer for electroplating
06/13/2006US7060616 Method of manufacturing semiconductor device
06/13/2006US7060615 Methods of forming roughened layers of platinum
06/13/2006US7060614 Method for forming film
06/13/2006US7060613 Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding
06/13/2006US7060612 Method of adjusting resistors post silicide process
06/13/2006US7060611 Method for manufacturing electric device for signal transmission
06/13/2006US7060610 Method for forming contact in semiconductor device
06/13/2006US7060609 Method of manufacturing a semiconductor device
06/13/2006US7060608 System and method for filling openings in semiconductor products
06/13/2006US7060607 Circuit method integrating the power distribution functions of the circuits and leadframes into the chip surface
06/13/2006US7060606 Method and apparatus for chemical mechanical polishing of semiconductor substrates
06/13/2006US7060605 Methods for making dual-damascene dielectric structures
06/13/2006US7060604 Multilayer wiring substrate, and method of producing same
06/13/2006US7060603 Methods of forming metal wiring of semiconductor devices including sintering the wiring layers and forming a via hole with a barrier metal
06/13/2006US7060602 Method of manufacturing electronic part and mounting electronic part
06/13/2006US7060601 Packaging substrates for integrated circuits and soldering methods
06/13/2006US7060600 Semiconductor capacitor and MOSFET fitted therewith
06/13/2006US7060599 Method of forming shallow doped junctions having a variable profile gradation of dopants
06/13/2006US7060598 Method for implanting ions into semiconductor substrate
06/13/2006US7060597 Manufacturing method for a silicon substrate having strained layer
06/13/2006US7060596 Process for fabricating a single-crystal substrate and integrated circuit comprising such a substrate
06/13/2006US7060595 Circuit substrate and fabrication method thereof
06/13/2006US7060594 Memory device and method of manufacturing including deuterated oxynitride charge trapping structure
06/13/2006US7060593 Method of and mechanism for peeling adhesive tape bonded to segmented semiconductor wafer
06/13/2006US7060592 Image sensor and fabricating method thereof
06/13/2006US7060591 Method for fabricating a semiconductor device by transferring a layer to a support with curvature
06/13/2006US7060590 Layer transfer method
06/13/2006US7060589 Method for manufacturing a semiconductor integrated circuit device that includes covering the bottom of an isolation trench with spin-on glass and etching back the spin-on glass to a predetermined depth
06/13/2006US7060588 Semiconductor device using shallow trench isolation and method of fabricating the same
06/13/2006US7060587 Method for forming macropores in a layer and products obtained thereof
06/13/2006US7060586 PCMO thin film with resistance random access memory (RRAM) characteristics
06/13/2006US7060585 Hybrid orientation substrates by in-place bonding and amorphization/templated recrystallization
06/13/2006US7060584 Process to improve high performance capacitor properties in integrated MOS technology
06/13/2006US7060583 Method for manufacturing a bipolar transistor having a polysilicon emitter
06/13/2006US7060582 Adjusting the germanium concentration of a semiconductor layer for equal thermal expansion for a hetero-junction bipolar transistor device
06/13/2006US7060581 Method for manufacturing a semiconductor device
06/13/2006US7060580 Field effect transistor and method of fabricating the same
06/13/2006US7060579 Increased drive current by isotropic recess etch
06/13/2006US7060578 Semiconductor device and method of fabricating the same
06/13/2006US7060577 Method for forming metal silicide layer in active area of semiconductor device
06/13/2006US7060576 Epitaxially deposited source/drain
06/13/2006US7060575 Semiconductor device having transistor and method of manufacturing the same
06/13/2006US7060574 Buried channel type transistor having a trench gate and method of manufacturing the same
06/13/2006US7060573 Extended poly buffer STI scheme
06/13/2006US7060572 MOSFET with short channel structure and formation method thereof
06/13/2006US7060571 Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric
06/13/2006US7060570 Methods of fabricating multiple sets of field effect transistors
06/13/2006US7060569 Methods of fabricating multiple sets of field effect transistors
06/13/2006US7060568 Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit
06/13/2006US7060567 Method for fabricating trench power MOSFET
06/13/2006US7060566 Standby current reduction over a process window with a trimmable well bias
06/13/2006US7060565 Fabrication of dielectric for a nonvolatile memory cell having multiple floating gates
06/13/2006US7060564 Memory device and method of simultaneous fabrication of core and periphery of same
06/13/2006US7060563 Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturing the same
06/13/2006US7060562 Method for fabricating gate electrodes in a field plate trench transistor, and field plate trench transistor
06/13/2006US7060561 Method for fabricating memory device
06/13/2006US7060560 Method of manufacturing non-volatile memory cell
06/13/2006US7060559 Method of manufacturing a nonvolatile semiconductor memory device
06/13/2006US7060558 Method for fabricating a field-effect transistor having a floating gate
06/13/2006US7060557 Fabrication of high-density capacitors for mixed signal/RF circuits
06/13/2006US7060556 Drain extended MOS transistors with multiple capacitors and methods of fabrication