Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2006
06/15/2006US20060128160 Photoresist strip using solvent vapor
06/15/2006US20060128159 Method of removing etch residues
06/15/2006US20060128158 Repetively dry-etching a sacrificial layer of silicon dioxide on a silicon substrate with etching gas, a hydrogen fluoride/methanol mixture, to form structures and grooves and to generate reaction products including water which is removed; capacitance type acceleration sensor 100; cost efficiency
06/15/2006US20060128157 Semiconductor structure with partially etched gate and method of fabricating the same
06/15/2006US20060128156 Self-patterning of photo-active dielectric materials for interconnect isolation
06/15/2006US20060128155 Columnar structured material, electrode having columnar structured material, and production method therefor
06/15/2006US20060128154 Glass substrate for magnetic disk and its production process
06/15/2006US20060128153 Method for cleaning slurry particles from a surface polished by chemical mechanical polishing
06/15/2006US20060128152 Plasma oxidation and removal of oxidized material
06/15/2006US20060128151 Method for removing photoresist layer and method for forming metal line in semiconductor device using the same
06/15/2006US20060128150 Ruthenium as an underlayer for tungsten film deposition
06/15/2006US20060128149 Method for forming a metal wiring in a semiconductor device
06/15/2006US20060128148 Method of manufacturing semiconductor device
06/15/2006US20060128147 Method of fabricating electrically conducting vias in a silicon wafer
06/15/2006US20060128146 Method of forming barrier layer and method of fabricating interconnect
06/15/2006US20060128145 Device having dual etch stop liner and reformed silicide layer and related methods
06/15/2006US20060128144 Interconnects having a recessed capping layer and methods of fabricating the same
06/15/2006US20060128143 Production method for electronic component and electronic component
06/15/2006US20060128142 Method for selective deposition of a thin self-assembled monolayer
06/15/2006US20060128141 Semiconductor device and method for fabricating the same
06/15/2006US20060128140 Method of forming a contact hole in a semiconductor device
06/15/2006US20060128139 Process sequence for doped silicon fill of deep trenches
06/15/2006US20060128138 Gate structure having diffusion barrier layer
06/15/2006US20060128137 Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes
06/15/2006US20060128136 Systems and methods for solder bonding
06/15/2006US20060128135 Solder bump composition for flip chip
06/15/2006US20060128134 Method for re-routing lithography-free microelectronic devices
06/15/2006US20060128133 Activated electroless plating reagent is applied to a substrate in the chamber under conditions to cause the metal of the electroless plating reagent to deposit on the substrate; uniformity and superior surface quality
06/15/2006US20060128132 Method and system for controlling the presence of fluorine in refractory metal layers
06/15/2006US20060128131 Independently accessed double-gate and tri-gate transistors in same process flow
06/15/2006US20060128130 Method for fabricating recessed gate structure
06/15/2006US20060128129 Nanometer-scale memory device utilizing self-aligned rectifying elements and method of making
06/15/2006US20060128128 Method for producing a conductive layer
06/15/2006US20060128127 Method of depositing a metal compound layer and apparatus for depositing a metal compound layer
06/15/2006US20060128126 Masked sidewall implant for image sensor
06/15/2006US20060128125 Gate Electrodes and the Formation Thereof
06/15/2006US20060128124 Growth of reduced dislocation density non-polar gallium nitride by hydride vapor phase epitaxy
06/15/2006US20060128123 Methods of forming integrated circuits structures including epitaxial silicon layers in a active regions
06/15/2006US20060128122 Mbe growth of a semiconductor layer structure
06/15/2006US20060128121 Laser dicing apparatus for a gallium arsenide wafer and method thereof
06/15/2006US20060128120 Short-wavelength laser dicing apparatus for a diamond wafer and dicing method thereof
06/15/2006US20060128119 Semiconductor device fabrication method
06/15/2006US20060128118 Nitride semiconductor device comprising bonded substrate and fabrication method of the same
06/15/2006US20060128117 Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
06/15/2006US20060128116 Manufacturing method of silicon on insulator wafer
06/15/2006US20060128115 Method for forming a shallow trench isolation structure with reduced stress
06/15/2006US20060128114 Trench isolation type semiconductor device and method of fabricating the same
06/15/2006US20060128113 Technique and methodology to passivate inductively or capacitively coupled surface currents under capacitor structures
06/15/2006US20060128112 Technique and methodology to passivate inductively coupled surface currents
06/15/2006US20060128111 Raised sti process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain
06/15/2006US20060128110 Semiconductor device and a method of manufacturing the same
06/15/2006US20060128109 Method of manufacturing a metal-insulator-metal capacitor
06/15/2006US20060128108 Method for forming a titanium nitride layer and method for forming a lower electrode of a MIM capacitor using the titanium nitride layer
06/15/2006US20060128107 Methods of forming memory devices
06/15/2006US20060128106 Transistor and method for manufacturing thereof
06/15/2006US20060128105 High mobility heterojunction complementary field effect transistors and methods thereof
06/15/2006US20060128104 NROM memory cell, memory array, related devices and methods
06/15/2006US20060128103 NROM memory cell, memory array, related devices and methods
06/15/2006US20060128102 Manufacturing method of an non-volatile memory cell
06/15/2006US20060128101 Memory package
06/15/2006US20060128100 Semiconductor device and a method of producing the same
06/15/2006US20060128099 Method of fabricating flash memory device including control gate extensions
06/15/2006US20060128098 Split gate type nonvolatile semiconductor memory device, and method of fabricating the same
06/15/2006US20060128097 Nonvolatile memory cells with buried channel transistors
06/15/2006US20060128096 Methods of forming semiconductor devices
06/15/2006US20060128095 Semiconductor device comprising a highly-reliable, constant capacitance capacitor
06/15/2006US20060128094 Semiconductor integrated circuit device and method of manufacturing the same
06/15/2006US20060128093 Method of manufacturing semiconductor device
06/15/2006US20060128092 Wafer bonded MOS decoupling capacitor
06/15/2006US20060128091 Device having enhanced stress state and related methods
06/15/2006US20060128090 Latch-up prevention for memory cells
06/15/2006US20060128089 Method of manufacturing a semiconductor device and semiconductor device obtained by means of such a method
06/15/2006US20060128088 Vertical integrated component, component arrangement and method for production of a vertical integrated component
06/15/2006US20060128087 Methods and devices for improved charge management for three-dimensional and color sensing
06/15/2006US20060128086 Device having dual etch stop liner and protective layer and related methods
06/15/2006US20060128085 Metal-oxide-semiconductor device having improved performance and reliability
06/15/2006US20060128084 Method of forming a gate pattern in a semiconductor device
06/15/2006US20060128083 Method for fabricating organic thin film transistor
06/15/2006US20060128082 Gate control and endcap improvement
06/15/2006US20060128081 MIS semiconductor device and method of fabricating the same
06/15/2006US20060128080 Manufacturing method of semiconductor device
06/15/2006US20060128079 Method for manufacturing a thin film transistor
06/15/2006US20060128078 SOI substrate manufacturing method
06/15/2006US20060128077 Thin film transistor and method for manufacturing the same
06/15/2006US20060128076 Self-aligning patterning method
06/15/2006US20060128075 Manufacturing method of silicon on insulator wafer
06/15/2006US20060128074 Combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted silicon-on-insulator (PD-SOI)devices
06/15/2006US20060128073 Multiple-wavelength laser micromachining of semiconductor devices
06/15/2006US20060128072 Method of protecting fuses in an integrated circuit die
06/15/2006US20060128071 Integrated antifuse structure for finfet and cmos devices
06/15/2006US20060128070 Non-volatile memory device and fabricating method thereof
06/15/2006US20060128069 Package structure with embedded chip and method for fabricating the same
06/15/2006US20060128068 Methods of using sonication to couple a heat sink to a heat-generating component
06/15/2006US20060128067 Semiconductor device package
06/15/2006US20060128066 Flexible carrier and release method for high volume electronic package fabrication
06/15/2006US20060128065 Sheet can be stuck to a wafer at low temperatures of 100 degrees C. or below, is soft to the extent that it can be handled at room temperature, and can be cut simultaneously with a wafer under usual cutting conditions
06/15/2006US20060128064 Wafer packaging and singulation method
06/15/2006US20060128063 Method of manufacturing semiconductor device and support structure for semiconductor substrate
06/15/2006US20060128062 Electrical or electronic component and method of producing same
06/15/2006US20060128061 Fabrication of stacked die and structures formed thereby