Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2006
06/20/2006US7064566 Probe card assembly and kit
06/20/2006US7064512 Positioning apparatus, exposure apparatus, and semiconductor device manufacturing method
06/20/2006US7064491 Ion implantation system and control method
06/20/2006US7064453 Semiconductor memory device including a gate electrode with a recess
06/20/2006US7064452 Package structure with a retarding structure and method of making same
06/20/2006US7064447 Bond pad structure comprising multiple bond pads with metal overlap
06/20/2006US7064446 Under bump metallization layer to enable use of high tin content solder bumps
06/20/2006US7064445 Wafer level testing and bumping process
06/20/2006US7064444 Multi-chip ball grid array package
06/20/2006US7064441 Semiconductor device and method of manufacturing the same
06/20/2006US7064440 Semiconductor device
06/20/2006US7064439 Integrated electrical circuit and method for fabricating it
06/20/2006US7064437 Semiconductor device having aluminum conductors
06/20/2006US7064436 Semiconductor device and method of fabricating the same
06/20/2006US7064434 Customized microelectronic device and method for making customized electrical interconnections
06/20/2006US7064433 Multiple-ball wire bonds
06/20/2006US7064432 Method and system for bonding a semiconductor chip onto a carrier using micro-pins
06/20/2006US7064429 Electronic package having integrated cooling element with clearance for engaging package
06/20/2006US7064425 Semiconductor device circuit board, and electronic equipment
06/20/2006US7064420 Integrated circuit leadframe with ground plane
06/20/2006US7064417 Semiconductor device including a bipolar transistor
06/20/2006US7064416 Semiconductor device and method having multiple subcollectors formed on a common wafer
06/20/2006US7064413 Fin-type resistors
06/20/2006US7064412 Electronic package with integrated capacitor
06/20/2006US7064408 Schottky barrier diode and method of making the same
06/20/2006US7064402 Magnetic random access memory
06/20/2006US7064401 Thin film piezoelectric element, method of manufacturing the same, and actuator
06/20/2006US7064400 Semiconductor device and process for producing the same
06/20/2006US7064399 Advanced CMOS using super steep retrograde wells
06/20/2006US7064398 Semiconductor memory device
06/20/2006US7064396 Integrated circuit with multiple spacer insulating region widths
06/20/2006US7064395 Semiconductor device and method for fabricating the same
06/20/2006US7064394 Nonvolatile semiconductor memory device
06/20/2006US7064393 Electrostatic discharge protection structures having high holding current for latch-up immunity
06/20/2006US7064392 Semiconductor device
06/20/2006US7064391 Bond and back side etchback transistor fabrication process
06/20/2006US7064390 Metal gate engineering for surface p-channel devices
06/20/2006US7064389 Semiconductor memory device having full depletive type logic transistors and partial depletion type memory transistors
06/20/2006US7064388 Semiconductor device and method for manufacturing the same
06/20/2006US7064387 Silicon-on-insulator (SOI) substrate and method for manufacturing the same
06/20/2006US7064386 Thin film transistor and fabricating method thereof
06/20/2006US7064385 DMOS-transistor with lateral dopant gradient in drift region and method of producing the same
06/20/2006US7064383 Non-volatile memory device
06/20/2006US7064382 Nonvolatile memory and nonvolatile memory manufacturing method
06/20/2006US7064381 Non-volatile memory device having upper and lower trenches and method for fabricating the same
06/20/2006US7064380 Semiconductor device and a method of manufacturing the same
06/20/2006US7064379 Nonvolatile semiconductor memory device
06/20/2006US7064378 Local-length nitride SONOS device having self-aligned ONO structure and method of manufacturing the same
06/20/2006US7064377 Flash memory cell with buried floating gate and method for operating such a flash memory cell
06/20/2006US7064376 High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
06/20/2006US7064375 Semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof
06/20/2006US7064374 Barrier layers for protecting metal oxides from hydrogen degradation
06/20/2006US7064373 Architecture and fabrication method of a vertical memory cell
06/20/2006US7064372 Large-area nanoenabled macroelectronic substrates and uses therefor
06/20/2006US7064371 Low leakage one transistor static random access memory
06/20/2006US7064370 Method for manufacturing semiconductor device and the device thereof
06/20/2006US7064369 Method for manufacturing a semiconductor device including a PIP capacitor and a MOS transistor
06/20/2006US7064367 Magnetoresistive element, magnetic memory cell, and magnetic memory device
06/20/2006US7064366 Ferroelectric memory devices having an expanded plate electrode
06/20/2006US7064365 Ferroelectric capacitors including a seed conductive film
06/20/2006US7064364 Thin film transistor and method for manufacturing the same
06/20/2006US7064363 Symmetric inducting device for an integrated circuit having a ground shield
06/20/2006US7064361 NPN transistor having reduced extrinsic base resistance and improved manufacturability
06/20/2006US7064360 Bipolar transistor and method for fabricating it
06/20/2006US7064353 LED chip with integrated fast switching diode for ESD protection
06/20/2006US7064352 Diamond semiconductor device and method for manufacturing the same
06/20/2006US7064351 Circuit array substrate
06/20/2006US7064347 Thin film transistor substrate for display device and fabricating method thereof
06/20/2006US7064346 Transistor and semiconductor device
06/20/2006US7064344 Barrier material encapsulation of programmable material
06/20/2006US7064324 Charged particle beam apparatus
06/20/2006US7064240 Contacting organic compound and a fluorine gas, heating, controlling the content of an oxygen gas within the reaction system to 2% by volume or less to produce a perfluorocarbon reduced in the content of impurities
06/20/2006US7064224 Organometallic complexes and their use as precursors to deposit metal films
06/20/2006US7064090 Method of manufacturing a semiconductor integrated circuit device
06/20/2006US7064089 Plasma treatment apparatus and method for plasma treatment
06/20/2006US7064088 Method for forming low-k hard film
06/20/2006US7064087 Phosphorous-doped silicon dioxide process to customize contact etch profiles
06/20/2006US7064086 Method for producing optical film
06/20/2006US7064085 Feed forward spacer width control in semiconductor manufacturing
06/20/2006US7064084 Oxide film forming method
06/20/2006US7064083 Hexakis(monohydrocarbylamino)disilanes and method for the preparation thereof
06/20/2006US7064082 Methods for forming pin alloy-semiconductor devices with rectifying junction contacts
06/20/2006US7064081 Semiconductor device and method for producing the same
06/20/2006US7064080 Semiconductor processing method using photoresist and an antireflective coating
06/20/2006US7064079 Method of removing polymer and apparatus for doing the same
06/20/2006US7064078 Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme
06/20/2006US7064077 Method for high aspect ratio HDP CVD gapfill
06/20/2006US7064076 Process for low temperature, dry etching, and dry planarization of copper
06/20/2006US7064075 Method for manufacturing semiconductor electronics devices
06/20/2006US7064074 Technique for forming contacts for buried doped regions in a semiconductor device
06/20/2006US7064073 Technique for reducing contaminants in fabrication of semiconductor wafers
06/20/2006US7064072 Method for fabricating trench isolation
06/20/2006US7064071 Method of forming a conformal spacer adjacent to a gate electrode structure
06/20/2006US7064070 Removal of CMP and post-CMP residue from semiconductors using supercritical carbon dioxide process
06/20/2006US7064069 Substrate thinning including planarization
06/20/2006US7064068 Method to improve planarity of electroplated copper
06/20/2006US7064067 Reduction of lateral silicide growth in integrated circuit technology
06/20/2006US7064066 Method for making a semiconductor device having a high-k gate dielectric and a titanium carbide gate electrode
06/20/2006US7064065 Silver under-layers for electroless cobalt alloys
06/20/2006US7064064 Copper recess process with application to selective capping and electroless plating