Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2006
06/14/2006EP1670045A2 Gate of a memory transistor with a ferroelectric layer and method of manufacturing the same
06/14/2006EP1670044A1 Production method for silicon epitaxial wafer, and silicon epitaxial wafer
06/14/2006EP1670043A2 Exposure apparatus, exposure method, and device manufacturing method
06/14/2006EP1670041A1 Exposure method and apparatus, and device manufacturing method
06/14/2006EP1670040A1 Projection exposure device, projection exposure method, and device manufacturing method
06/14/2006EP1670039A1 Exposure apparatus and device producing method
06/14/2006EP1670038A1 Optical element and exposure device
06/14/2006EP1669808A2 Substrate placement in immersion lithography
06/14/2006EP1669803A2 Novel copolymers and photoresist compositions comprising copolymer resin binder component
06/14/2006EP1669389A1 Crosslinkable fluoroaromatic prepolymer and use thereof
06/14/2006EP1668710A1 Light emitting diode with porous sic substrate and method for fabricating
06/14/2006EP1668706A2 Structure and method for metal replacement gate of high performance device
06/14/2006EP1668705A1 Heterojunction bipolar transistor with tunnelling mis emitter junction
06/14/2006EP1668703A1 Dynamic control of capacitance elements in field effect semiconductor devices
06/14/2006EP1668699A2 Method of forming a semiconductor package and structure thereof
06/14/2006EP1668696A1 Method for separately optimizing thin gate dielectric of pmos and nmos transistors within the same semiconductor chip and device manufactured thereby
06/14/2006EP1668695A1 Method and apparatus for fabricating cmos field effect transistors
06/14/2006EP1668694A1 Semiconductor device, method of manufacturing same, identification label and information carrier
06/14/2006EP1668693A1 Indirect bonding with disappearance of the bonding layer
06/14/2006EP1668692A2 Adjustable self-aligned air gap dielectric for low capacitance wiring
06/14/2006EP1668691A2 Method for forming a semiconductor device having isolation regions
06/14/2006EP1668690A2 Electric ultimate defects analyzer detecting all defects in pcb/mcm
06/14/2006EP1668689A2 Process and integration scheme for fabricating conductive components through-vias and semiconductor components including conductive through-wafer vias
06/14/2006EP1668687A1 Fabrication of conductive metal layer on semiconductor devices
06/14/2006EP1668686A2 Reversible leadless package and methods of making and using same
06/14/2006EP1668685A1 Integrated electronic chip and interconnect device and process for making the same
06/14/2006EP1668684A1 Transparent amorphous carbon structure in semiconductor devices
06/14/2006EP1668683A1 Method of forming dielectric layers with low dielectric constants
06/14/2006EP1668682A2 Growth of high-k dielectrics by atomic layer deposition
06/14/2006EP1668681A1 A semiconductor device having a nickel/cobalt silicide region formed in a silicon region
06/14/2006EP1668680A1 Method for the production of a hard mask and hard mask arrangement
06/14/2006EP1668679A1 Illumination optical system and exposure apparatus using the same
06/14/2006EP1668678A1 Capacitor constructions, rugged silicon-containing surfaces, and methods of forming rugged silicon-containing surfaces
06/14/2006EP1668677A1 A device and a method for forming a capacitor device
06/14/2006EP1668676A1 Method for forming ferrocapacitors and feram devices
06/14/2006EP1668675A1 Method for forming vertical ferroelectric capacitors
06/14/2006EP1668673A2 Semiconductor device and making thereof
06/14/2006EP1668672A2 Structure and method of making strained channel cmos transistors having lattice-mismatched epitaxial extension and source and drain regions
06/14/2006EP1668668A2 Deposition of silicon-containing films from hexachlorodisilane
06/14/2006EP1668416A2 Method and apparatus for protecting a reticle used in chip production from contamination
06/14/2006EP1668174A2 Plating method and apparatus
06/14/2006EP1668168A2 Control system for a sputtering system
06/14/2006EP1625409A4 Planarizing and testing of bga packages
06/14/2006EP1622819A4 Tray carrier with ultraphobic surfaces
06/14/2006EP1618035A4 Microfluidic device with ultraphobic surfaces
06/14/2006EP1613866A4 Fluid handling component with ultraphobic surfaces
06/14/2006EP1613541A4 Carrier with ultraphobic surfaces
06/14/2006EP1590836A4 Mram cells having magnetic write lines with a stable magnetic state at the end regions
06/14/2006EP1535290A4 Nanoporous materials and methods of formation thereof
06/14/2006EP1459354B1 Retaining device, especially for fixing a semiconductor wafer in a plasma etching device, and method for supplying heat to or discharging heat from a substrate
06/14/2006EP1446805B8 Electrodes, method and apparatus for memory structure
06/14/2006EP1438447B1 Method and conveyorized system for electrolytically processing work pieces
06/14/2006EP1381663B1 Cleaning compositions
06/14/2006EP1240672B1 Production of single-pole components
06/14/2006EP1234327A4 Reactor for processing a semiconductor wafer
06/14/2006EP1206399A4 Protective system for integrated circuit (ic) wafers
06/14/2006EP1142011B1 Method of forming devices with graded top oxide and graded drift region
06/14/2006EP1141444B1 Novel composition for selective etching of oxides over metals
06/14/2006EP1125328B1 Method for producing a dram cell arrangement
06/14/2006EP1103071A4 Detection of nontransient processing anomalies in vacuum manufacturing process
06/14/2006EP1042818B1 Coulomb blockade multilevel memory device and corresponding methods of making and operating the same
06/14/2006EP1025583B1 Improved gapfill of semiconductor structure using doped silicate glasses with multi-step deposition/anneal process
06/14/2006EP1024965B1 Process for removing residues from a semiconductor substrate
06/14/2006EP0988116A4 High efficiency photoresist coating
06/14/2006EP0966761B1 Vertical igbt with an soi structure
06/14/2006EP0956142B1 Liquid cooled trap
06/14/2006EP0871979B1 Method of manufacturing a silicon photovoltaic cell and cell obtained by this method
06/14/2006DE20221268U1 Chamber for use with gas delivery apparatus for atomic layer deposition, includes chamber lid having bottom surface that is shaped and sized to cover receiving surface of substrate support
06/14/2006DE19948455B4 Vorrichtung und Verfahren zum Positionieren und Bestücken eines Bauelements in Oberflächen-Montagetechnik Apparatus and method for positioning and loading a component in surface mount technology
06/14/2006DE19943385B4 Verfahren zur Herstellung einer elektrischen Verbindung zwischen der Vorder- und Rückseite von Halbleiterchips A method for making an electrical connection between the front and back of the semiconductor chip
06/14/2006DE19921259B4 Nichtflüchtiger ferroelektrischer Speicher Non-volatile ferroelectric memory
06/14/2006DE19781956B4 Verfahren zum Aufbringen einer planarisierten dielektrischen Schicht auf einem Halbleitersubstrat A method of applying a planarized dielectric layer on a semiconductor substrate
06/14/2006DE112004000877T5 Verfahren zur Herstellung von Widerstandsstrukturen A method of manufacturing resistive structures
06/14/2006DE112004000060T5 Schaltelement, Verfahren zum Ansteuern des Schaltelements, überschreibbare integrierte Logikschaltung und Speicherelement Switching element, method of driving the switching element, rewritable logic integrated circuit memory element, and
06/14/2006DE10358325B4 Verfahren zum Herstellen einer integrierten Halbleiterschaltungsanordnung A method of manufacturing a semiconductor integrated circuit arrangement
06/14/2006DE10350510B4 Integrierte Schaltungsvorrichtungen mit Sicherungsstrukturen, die Pufferschichten enthalten, und Verfahren zur Herstellung derselben Integrated circuit devices with fuse structures comprising buffer layers and methods for making the same
06/14/2006DE10317268B4 Verfahren zur fehlerfreien Medieneingabe in Halbleiterherstellungsprozessen A method for error-free media input in semiconductor manufacturing processes
06/14/2006DE10309998B4 Halbleiterbauelement mit einer verstärkten Substruktur einer Kontaktstelle und zugehöriges Herstellungsverfahren A semiconductor device with a reinforced substructure of a contact point and associated production method
06/14/2006DE10260344B4 Magnetische Dünnfilmspeichervorrichtung, die Daten mit bidirektionalem Strom schreibt Thin film magnetic memory device which writes data with bidirectional current
06/14/2006DE10255849B4 Verbesserte Drain/Source-Erweiterungsstruktur eines Feldeffekttransistors mit dotierten Seitenwandabstandselementen mit hoher Permittivität und Verfahren zu deren Herstellung Improved drain / source extension structure of a field effect transistor having the doped sidewall spacers with high permittivity and processes for their preparation
06/14/2006DE10231965B4 Verfahren zur Herstellung einer T-Gate-Struktur sowie eines zugehörigen Feldeffekttransistors A method for preparing a T-gate structure as well as of an associated field effect transistor
06/14/2006DE10230088B4 Verfahren zum Herstellen einer Halbleitervorrichtung A method of manufacturing a semiconductor device
06/14/2006DE10220921B4 Verfahren zur Herstellung eines Halbleiterelements A process for producing a semiconductor element
06/14/2006DE102005052504A1 Verfahren zum Laserbearbeiten eines Wafers Method of laser processing a wafer
06/14/2006DE102005029313A1 Manufacture of semiconductor device by forming polysilicon layer on buried oxide film, and implanting impurity into second silicon epitaxial layer and polysilicon layer to form source/drain region
06/14/2006DE102005012396B3 Semiconductor chip e.g. flip-chip, mounting method for use on substrate, involves taking chips from sprinkler station and feeding to mounting station, where chips are again taken from initialization station and placed in sprinkler station
06/14/2006DE102005007423B3 Integration of electronic component (8) into substrate by formation of dielectric insulating layers on substrate front side useful in structural element modelling in semiconductor flip-chip technology with photoresistive layer in cavity
06/14/2006DE102005003127B3 Lateral semiconductor component, such as IGBT-transistors and MOSFET and JFET, has drift regions of drift zone extending in lateral direction
06/14/2006DE102004061327A1 Vertikaler Bipolartransistor A vertical bipolar transistor
06/14/2006DE102004060171A1 Charge-trapping-Speicherzelle und Herstellungsverfahren Charge-trapping memory cell, and manufacturing method
06/14/2006DE102004059651A1 Crystalline layer on a Si substrate, is formed by epitaxial precipitation on a porous region of the substrate
06/14/2006DE102004059505A1 Anordnung zum Test von eingebetteten Schaltungen mit Hilfe von Testinseln Arrangement for testing embedded circuits using test Islands
06/14/2006DE102004059123A1 Substrate e.g. glass substrate, thinning device, has determining unit finding thinning period value based on sensor unit`s output value, thickness target value and auxiliary value specified based on difference in output and target values
06/14/2006DE102004058958A1 Material mit hoher Bandlücke und Dielektrizitätskonstante Material with a high dielectric constant and band gap
06/14/2006DE102004058878A1 Halbleiterbauelement und Verfahren zum Herstellen eines Halbleiterbauelements A semiconductor device and method of manufacturing a semiconductor device
06/14/2006DE102004004846B4 Verfahren zum Abscheiden einer Schicht aus einem Material auf einem Substrat A method of depositing a layer of a material on a substrate
06/14/2006DE10131625B4 Verfahren zum Herstellen eines FeRAM-Speichers A method of manufacturing a FeRAM memory
06/14/2006DE10116875B4 Verfahren zur Herstellung eines integrierten ferroelektrischen Speichers A process for producing an integrated ferroelectric memory
06/14/2006DE10050050B4 Verfahren zur Verringerung des Belastungseffekts beim Ätzen tiefer Gräben Process for reducing the loading effect during etching deep trenches
06/14/2006DE10004436B4 Greifer für eine Aufnahmevorrichtung einer Handhabungsvorrichtung für IC-Module Gripper for a receiving device of a handling device for IC modules