Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2006
06/20/2006US7064063 Photo-thermal induced diffusion
06/20/2006US7064062 Incorporating dopants to enhance the dielectric properties of metal silicates
06/20/2006US7064061 Process for fabricating interconnect networks
06/20/2006US7064060 Method for manufacturing semiconductor device
06/20/2006US7064059 Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer
06/20/2006US7064058 Low-temperature growth high-quality ultra-thin praseodymium gate dieletrics
06/20/2006US7064057 Method and apparatus for localized material removal by electrochemical polishing
06/20/2006US7064056 Barrier layer stack to prevent Ti diffusion
06/20/2006US7064055 Method of forming a multi-layer semiconductor structure having a seamless bonding interface
06/20/2006US7064054 Contact structure and manufacturing method thereof
06/20/2006US7064053 Process for fabricating an electrical circuit comprising a polishing step
06/20/2006US7064052 Method of processing a transistor gate dielectric film with stem
06/20/2006US7064051 Method of forming self-aligned contact pads of non-straight type semiconductor memory device
06/20/2006US7064050 Metal carbide gate structure and method of fabrication
06/20/2006US7064049 Ion implantation method, SOI wafer manufacturing method and ion implantation system
06/20/2006US7064048 Method of forming a semi-insulating region
06/20/2006US7064047 Semiconductor device having a ball grid array and a fabrication process thereof
06/20/2006US7064046 Manufacturing method of semiconductor device
06/20/2006US7064045 Laser based method and device for forming spacer structures for packaging optical reflection devices
06/20/2006US7064044 Contact etching utilizing multi-layer hard mask
06/20/2006US7064043 Wafer bonded MOS decoupling capacitor
06/20/2006US7064042 Self aligned compact bipolar junction transistor layout, and method of making same
06/20/2006US7064041 Semiconductor device and manufacturing method therefor
06/20/2006US7064040 Method of fabricating semiconductor device
06/20/2006US7064039 Method to produce localized halo for MOS transistor
06/20/2006US7064038 Semiconductor device and method for fabricating the same
06/20/2006US7064037 Silicon-germanium virtual substrate and method of fabricating the same
06/20/2006US7064036 Dual-gate transistor device and method of forming a dual-gate transistor device
06/20/2006US7064035 Mask ROM and fabrication thereof
06/20/2006US7064034 Technique for fabricating logic elements using multiple gate layers
06/20/2006US7064033 Semiconductor device and method of manufacturing same
06/20/2006US7064032 Method for forming non-volatile memory cell with low-temperature-formed dielectric between word and bit lines, and non-volatile memory array including such memory cells
06/20/2006US7064031 Method for forming a semiconductor device
06/20/2006US7064030 Method for forming a multi-bit non-volatile memory device
06/20/2006US7064029 Semiconductor memory device and method of producing the same
06/20/2006US7064028 Semiconductor memory and method of producing the same
06/20/2006US7064027 Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance
06/20/2006US7064026 Semiconductor device having shared contact and fabrication method thereof
06/20/2006US7064025 Method for forming self-aligned dual salicide in CMOS technologies
06/20/2006US7064024 Semiconductor device and method of fabricating the same
06/20/2006US7064023 D/A converter circuit, semiconductor device incorporating the D/A converter circuit, and manufacturing method of them
06/20/2006US7064022 Method of forming merged FET inverter/logic gate
06/20/2006US7064021 Method for fomring a self-aligned LTPS TFT
06/20/2006US7064020 Method of manufacturing a semiconductor device having a gate electrode with a three layer structure
06/20/2006US7064019 Implanted asymmetric doped polysilicon gate FinFET
06/20/2006US7064018 Methods for fabricating three dimensional integrated circuits
06/20/2006US7064017 Method of forming a CMOS transistor
06/20/2006US7064016 Semiconductor device and method of fabricating thereof
06/20/2006US7064015 Semiconductor device and manufacturing method of the same
06/20/2006US7064014 Backside metallization on sides of microelectronic dice for effective thermal contact with heat dissipation devices
06/20/2006US7064013 Cap attach surface modification for improved adhesion
06/20/2006US7064012 Method of making a semiconductor chip assembly with a pillar and a routing line using multiple etch steps
06/20/2006US7064011 Semiconductor device fabricating apparatus and semiconductor device fabricating method
06/20/2006US7064010 Methods of coating and singulating wafers
06/20/2006US7064009 Thermally enhanced chip scale lead on chip semiconductor package and method of making same
06/20/2006US7064008 Semiconductor leadframes plated with thick nickel, minimum palladium, and pure tin
06/20/2006US7064007 Method of using foamed insulators in three dimensional multichip structures
06/20/2006US7064006 Multiple die stack apparatus employing T-shaped interposer elements
06/20/2006US7064005 Semiconductor apparatus and method of manufacturing same
06/20/2006US7064004 Induction-based heating for chip attach
06/20/2006US7064003 Memory package
06/20/2006US7064002 Method for fabricating interposers including upwardly protruding dams, semiconductor device assemblies including the interposers
06/20/2006US7064001 Method of production of semiconductor module with external connection terminal
06/20/2006US7064000 Methods of chemically assembled electronic nanotechnology circuit fabrication
06/20/2006US7063999 Thin film processing method and thin film processing apparatus including controlling the cooling rate to control the crystal sizes
06/20/2006US7063998 Image sensor having photo diode and method for manufacturing the same
06/20/2006US7063997 Process for producing nitride semiconductor light-emitting device
06/20/2006US7063996 Method for manufacturing a light emitting diode device
06/20/2006US7063995 Nitride semiconductor light emitting device and manufacturing method thereof
06/20/2006US7063994 Organic semiconductor devices and methods of fabrication including forming two parts with polymerisable groups and bonding the parts
06/20/2006US7063993 Method of fabricating devices incorporating microelectromechanical systems using at least one UV curable tape
06/20/2006US7063992 Semiconductor substrate surface preparation using high temperature convection heating
06/20/2006US7063991 Methods of determining characteristics of doped regions on device wafers, and system for accomplishing same
06/20/2006US7063989 Method of aligning a semiconductor substrate with a semiconductor alignment apparatus
06/20/2006US7063988 Circuit for detecting arcing in an etch tool during wafer processing
06/20/2006US7063987 Backside failure analysis of integrated circuits
06/20/2006US7063986 Room temperature ferromagnetic semiconductor grown by plasma enhanced molecular beam epitaxy and ferromagnetic semiconductor based device
06/20/2006US7063985 Method for fabricating sensor devices having improved switching properties
06/20/2006US7063984 pair of targets spaced apart from one another within a closed vacuum vessel, each having a sputtering surface facing the sputtering surface of the other target; and substrate holder to receive facing target sputtering a CMO on an electrode.
06/20/2006US7063981 Producing a thin film on a substrate by subjecting the substrate to repeated pulses of gas or vapor-phase reactants
06/20/2006US7063975 gate formed in a shallow trench between bases having a base depth on a substrate; shallow trench has a depth equal to or smaller than the base depth; higher breakdown voltage and lower forward voltage drop; configured to operate at 100-1200 Volts or more
06/20/2006US7063939 Nanoimprint lithography; pressing an embossed, transparent mold into a photoresist film applied to substrate to transfer the pattern of protrusions and recesses by deforming the resist; efficient development; nonseparating, dimensional stability if overexposed to developer and/or etchant; semiconductors
06/20/2006US7063933 A crosslinked polyetheramide based on aromatic dicarboxylic acids and a bis/aminophenoxyphenylene/methane which provides improved adhesion between a substrate having a pressure generating element formed for ejecting ink and an ink flow-path forming member which constitutes the printing head
06/20/2006US7063931 Positive photoresist composition with a polymer including a fluorosulfonamide group and process for its use
06/20/2006US7063930 A thinner, resist-removing composition comprising an inorganic alkali compound, an organic amine, an organic solvent, anionic and nonionic surfactants and water; removes residue on edges and backs of substrates for thin film transistor-liquid crystal displays and semiconductors; corrosion resistance
06/20/2006US7063922 Method and apparatus for dry-etching half-tone phase-shift films, half-tone phase-shift photomasks and method for the preparation thereof, and semiconductor circuits and method for the fabrication thereof
06/20/2006US7063920 Configuring an array of micro-mirrors in a deep ultraviolet maskless photolithography system by generating an ideal mask layout representative of image characteristics associated with a desired image; next, an equivalent mask is produced in accordance with an average intensity of the ideal mask layout
06/20/2006US7063919 Lithographic template having a repaired gap defect method of repair and use
06/20/2006US7063900 Two organic electroluminiscent materials (EL) emitting electromagnetic radiation (EM) of two different second wavelength and a phosphor optically coupled absorbs a portion of EM radiation, and that which in not absorbed is mixed with the EM radiation having the third spectrum; efficiency; simplification
06/20/2006US7063899 Compositional buffers for electronic ceramics containing volatile elements and the fabrication method
06/20/2006US7063871 CVD process capable of reducing incubation time
06/20/2006US7063869 Printing device and method of manufacturing a light emitting device
06/20/2006US7063798 Method for realizing microchannels in an integrated structure
06/20/2006US7063797 Mounting electronic components
06/20/2006US7063765 Adhesive sheet for affixation of a wafer and method for processing using the same
06/20/2006US7063762 immersion of polytetrafluoroethylene dielectric layers in solutions comprising electroconductive polymers and intermetallic seeding materials, then rinsing, drying and coppering to form printed circuits or laminated chip carriers; electronics
06/20/2006US7063756 Enhanced design and process for a conductive adhesive
06/20/2006US7063753 dispersing nanostructure tube powder containing solutions onto wafer surfaces and positioning the tubes using magnets to from semiconductor devices such as transistors
06/20/2006US7063751 electrical and electronic apparatus comprising silicon having silicon oxide films and grooves filled with single crystal diffusion layers, polished by heat treatment in oxidation resistance atmosphere under low pressure
06/20/2006US7063749 Scrubber with sonic nozzle