Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2007
05/31/2007WO2007013024A3 Flip-chip package with air cavity
05/31/2007WO2007008211A3 Magnetic porous photonic crystal particles and method of making
05/31/2007WO2007001855A3 A method of making a metal gate semiconductor device
05/31/2007WO2006133129A3 Nano-scale self assembly in spinels induced by jahn-teller distortion
05/31/2007WO2006128713A3 Optical imaging arrangement
05/31/2007WO2006127894A3 Deposition of tensile and compressive stressed materials
05/31/2007WO2006086114A3 Method of manufacturing a hermetic chamber with electrical feedthroughs
05/31/2007WO2006076152B1 Light emitting diode with conducting metal substrate
05/31/2007WO2006057709A8 Method for deposition of metal layers from metal carbonyl precursors
05/31/2007WO2006009782A3 Persistent p-type group ii-vi semiconductors
05/31/2007WO2005112101A3 Organometallic precursor compounds
05/31/2007WO2005045885A3 Anti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems
05/31/2007US20070124714 Method for designing semiconductor integrated circuit layout
05/31/2007US20070124190 Method and system for estimating supply impact on a firm under a global crisis
05/31/2007US20070124108 Structure, system and method for dimensionally unstable layer dimension measurement
05/31/2007US20070124012 Programmed material consolidation methods employing machine vision
05/31/2007US20070124010 Methods and apparatus for material control system interface
05/31/2007US20070123692 Reacting 2,2-bis(4-hydroxyphenyl)propane and 2-(4-hydroxyphenyl)-2-(2-hydroxyphenyl)propane with a diarylsulfone compound; contact lens
05/31/2007US20070123082 Interconnect Assemblies And Methods
05/31/2007US20070123063 Method of manufacturing a semiconductor integrated circuit device
05/31/2007US20070123062 Semiconductor device and method of manufacturing the same
05/31/2007US20070123061 Method of treating a substrate, method of processing a substrate using a laser beam, and arrangement
05/31/2007US20070123060 Method for the deposition of a film by CVD or ALD
05/31/2007US20070123059 Methods of internal stress reduction in dielectric films with chemical incorporation and structures formed thereby
05/31/2007US20070123058 Semiconductor device structures that include sacrificial, readily removable materials
05/31/2007US20070123057 Overvoltage protection materials and process for preparing same
05/31/2007US20070123056 Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer
05/31/2007US20070123055 Insulating material
05/31/2007US20070123054 Nanocoils, systems and methods for fabricating nanocoils
05/31/2007US20070123053 Self-aligned pitch reduction
05/31/2007US20070123052 Process sequence for photoresist stripping and cleaning of photomasks for integrated circuit manufacturing
05/31/2007US20070123051 Oxide etch with nh4-nf3 chemistry
05/31/2007US20070123050 Etch process used during the manufacture of a semiconductor device and systems including the semiconductor device
05/31/2007US20070123049 Semiconductor process and method for removing condensed gaseous etchant residues on wafer
05/31/2007US20070123048 Use of a plasma source to form a layer during the formation of a semiconductor device
05/31/2007US20070123047 Polishing machine, workpiece supporting table pad, polishing method and manufacturing method of semiconductor device
05/31/2007US20070123046 Continuous in-line monitoring and qualification of polishing rates
05/31/2007US20070123045 Method for the treatment of material, in particular in the fabrication of semiconductor components
05/31/2007US20070123044 Method of forming an insulating capping layer for a copper metallization layer by using a silane reaction
05/31/2007US20070123043 A semiconductor device comprising a copper alloy as a barrier layer in a copper metallization layer
05/31/2007US20070123042 Methods to form heterogeneous silicides/germanides in cmos technology
05/31/2007US20070123041 Apparatus and method for surface processing such as plasma processing
05/31/2007US20070123040 Method for forming storage node contact plug in semiconductor device
05/31/2007US20070123039 Electroless plating of metal caps for chalcogenide-based memory devices
05/31/2007US20070123038 Method for manufacturing semiconductor device
05/31/2007US20070123037 Method of forming pattern using fine pitch hard mask
05/31/2007US20070123036 Method of filling structures for forming via-first dual damascene interconnects
05/31/2007US20070123035 Method of manufacturing semiconductor device
05/31/2007US20070123034 Method for removing a passivation layer prior to depositing a barrier layer in a copper metallization layer
05/31/2007US20070123033 Method of Forming A Damascene Structure with Integrated Planar Dielectric Layers
05/31/2007US20070123032 Method for manufacturing a semiconductor device having a stepped through-hole
05/31/2007US20070123031 Method for production of semiconductor device
05/31/2007US20070123030 Semiconductor devices and methods of manufacturing semiconductor devices
05/31/2007US20070123029 Semiconductor device and method for manufacturing the same
05/31/2007US20070123028 Methods of forming low-k dielectric layers containing carbon nanostructures
05/31/2007US20070123027 Wiring forming method, wiring forming apparatus, and wiring board
05/31/2007US20070123026 Semiconductor device having high frequency components and manufacturing method thereof
05/31/2007US20070123025 Forming a barrier layer in joint structures
05/31/2007US20070123024 Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing
05/31/2007US20070123023 Method of forming dual interconnects in manufacturing MRAM cells
05/31/2007US20070123022 Semiconductor device manufacturing method
05/31/2007US20070123021 Circuit under pad structure and bonding pad process
05/31/2007US20070123020 Method for forming solder balls with a stable oxide layer by controlling the reflow ambient
05/31/2007US20070123019 Methods of forming carbon nanotubes in a wiring pattern and related devices
05/31/2007US20070123018 Electrically rewritable non-volatile memory element and method of manufacturing the same
05/31/2007US20070123017 Device with self aligned gaps for capacitance reduction
05/31/2007US20070123016 Device with gaps for capacitance reduction
05/31/2007US20070123015 Passive components in the back end of integrated circuits
05/31/2007US20070123014 Method for fabricating semiconductor device having flask type recess gate
05/31/2007US20070123013 Controlled process and resulting device
05/31/2007US20070123012 Plasma implantation of deuterium for passivation of semiconductor-device interfaces
05/31/2007US20070123011 Production process for high purity polycrystal silicon and production apparatus for the same
05/31/2007US20070123010 Technique for reducing crystal defects in strained transistors by tilted preamorphization
05/31/2007US20070123009 Technique for increasing adhesion of metallization layers by providing dummy vias
05/31/2007US20070123008 Method for controlling dislocation positions in silicon germanium buffer layers
05/31/2007US20070123007 Film-forming method and film-forming equipment
05/31/2007US20070123006 Semiconductor device and method of manufacturing the same
05/31/2007US20070123005 Film formation apparatus, method for forming film, and method for manufacturing photoelectric conversion device
05/31/2007US20070123004 Method and apparatus for forming a crystalline silicon thin film
05/31/2007US20070123003 Dielectric interface for group III-V semiconductor device
05/31/2007US20070123002 Wafer dividing method
05/31/2007US20070123001 System and method for separating and packaging integrated circuits
05/31/2007US20070123000 Dicing tape attaching apparatus and dicing tape attaching method
05/31/2007US20070122999 Method and apparatus for fabricating and connecting a semiconductor power switching device
05/31/2007US20070122998 Active silicon device on a cleaved silicon-on-insulator substrate
05/31/2007US20070122997 Controlled process and resulting device
05/31/2007US20070122996 Epitaxial semiconductor layer and method
05/31/2007US20070122995 Controlled process and resulting device
05/31/2007US20070122994 Nitride semiconductor light emitting element
05/31/2007US20070122993 Method of simultaneously fabricating isolation structures having rounded and unrounded corners
05/31/2007US20070122992 Electronic component manufacturing method and electronic component
05/31/2007US20070122991 Resistor element and manufacturing method thereof
05/31/2007US20070122990 Method for producing epitaxial wafer with buried diffusion layer and epitaxial wafer with buried diffusion layer
05/31/2007US20070122989 Epitaxial and polycrystalline growth of si1-x-ygexcy and si1-ycy alloy layers on si by uhv-cvd
05/31/2007US20070122988 Methods of forming semiconductor devices using embedded l-shape spacers
05/31/2007US20070122987 Method for fabricating an nmos transistor
05/31/2007US20070122986 Carbon nanotube field effect transistor and methods for making same
05/31/2007US20070122985 Formation of active area using semiconductor growth process without STI integration
05/31/2007US20070122984 Structure and method for manufacturing strained finfet
05/31/2007US20070122983 Multi-operational mode transistor with multiple-channel device structure
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