Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2007
12/27/2007WO2007147691A1 Bipolar transistor with dual shallow trench isolation and low base resistance
12/27/2007WO2007147670A1 Method for producing a silicon substrate having modified surface properties and a silicon substrate of said type
12/27/2007WO2007147470A1 Method for producing an injection-moulded part comprising an integrated flexible printed circuit board
12/27/2007WO2007147304A1 Immersion flow field maintenance system for immersion lithography machine
12/27/2007WO2007130368A3 Dielectric spacers for metal interconnects and method to form the same
12/27/2007WO2007117774A3 Method of separating a structure in a semiconductor device
12/27/2007WO2007109464A3 Methods for etching a bottom anti-reflective coating layer in dual damascene application
12/27/2007WO2007109090A3 Packaging of mems devices
12/27/2007WO2007092499A3 Method of forming gated, self-aligned micro-structures and nano-structures
12/27/2007WO2007087249A3 Wafer level packaging to lidded chips
12/27/2007WO2007083237A8 Integration of self-aligned trenches in-between metal lines
12/27/2007WO2007081624B1 Notch stop pulsing process for plasma processing system
12/27/2007WO2007076076A3 Gas coupler for substrate processing chamber
12/27/2007WO2007062199A3 Device and method for holding a substrate
12/27/2007WO2007053527A3 Projection display system including a high fill ratio silicon spatial light modulator
12/27/2007WO2007047095A3 Integrated chamber cleaning system
12/27/2007WO2007040816A3 Treatment of low dielectric constant films using a batch processing system
12/27/2007WO2007019049A3 Edge ring assembly with dielectric spacer ring
12/27/2007WO2007016477A3 Normally off iii-nitride semiconductor device having a programmable gate
12/27/2007WO2006107010A3 Positive photoresist composition, thick film photoresist laminate, method for producing thick film resist pattern, and method for producing connecting terminal
12/27/2007WO2006050192A3 Trench mosfet with deposited oxide
12/27/2007WO2004007634A3 Emissive, high charge transport polymers
12/27/2007US20070299172 Circuit-connecting material and circuit terminal connected structure and connecting method
12/27/2007US20070298623 Method for straining a semiconductor device
12/27/2007US20070298622 Producing Method of Semiconductor Device
12/27/2007US20070298621 Baking method of quartz products, computer program and storage medium
12/27/2007US20070298620 Surface treatment, sorting and assembling methods of microelectronic devices and storage structure thereof
12/27/2007US20070298619 Method for stripping photoresist
12/27/2007US20070298618 Forming a gate stack on a semiconductor substrate, forming a conformal silicon oxide layer on the semiconductor substrate using a low temperature cyclic method involving exposing the semiconductor substrate to a silicon containing precursor to form a seed layer ; forming a spacer layer; memory cells
12/27/2007US20070298617 Processing method
12/27/2007US20070298616 Method of forming a mask pattern for fabricating a semiconductor device
12/27/2007US20070298615 Pattern forming method and method of manufacturing semiconductor devices
12/27/2007US20070298614 Apparatus for etching wafer by single-wafer process and single wafer type method for etching wafer
12/27/2007US20070298613 Method of manufacturing suspension structure
12/27/2007US20070298612 Compositions and methods for polishing silicon nitride materials
12/27/2007US20070298611 Selective barrier slurry for chemical mechanical polishing
12/27/2007US20070298610 Method for producing electro-optical apparatus
12/27/2007US20070298609 Capping of metal interconnects in integrated circuit electronic devices
12/27/2007US20070298608 Forming a copper diffusion barrier
12/27/2007US20070298607 Method for copper damascence fill for forming an interconnect
12/27/2007US20070298606 Chemical-mechanical polishing method and apparatus
12/27/2007US20070298605 Method for forming planarizing copper in a low-k dielectric
12/27/2007US20070298604 Method for fabricating single-damascene structure, dual damascene structure, and opening thereof
12/27/2007US20070298603 Die configurations and methods of manufacture
12/27/2007US20070298602 Method for Applying Solder to Redistribution Lines
12/27/2007US20070298601 Method and System for Controlled Plating of Vias
12/27/2007US20070298600 Method of Fabricating Semiconductor Device and Semiconductor Device Fabricated Thereby
12/27/2007US20070298599 Method for fabricating multiple FETs of different types
12/27/2007US20070298598 Semiconductor device and method of fabricating semiconductor device
12/27/2007US20070298597 Method for manufacturing a semiconductor device having a doped silicon film
12/27/2007US20070298596 Method of removing a photoresist pattern, method of forming a dual polysilicon layer using the removing method and method of manufacturing a semiconductor device using the removing
12/27/2007US20070298595 Method for fabricating polysilicon film
12/27/2007US20070298594 Semiconductor device fabrication method
12/27/2007US20070298593 Epitaxy silicon on insulator (ESOI)
12/27/2007US20070298592 Method for manufacturing single crystalline gallium nitride material substrate
12/27/2007US20070298591 Epitaxial silicon wafer and method for fabricating the same
12/27/2007US20070298590 Methods and apparatus for depositing a microcrystalline silicon film for photovoltaic device
12/27/2007US20070298589 Method of producing bonded wafer
12/27/2007US20070298588 Transfer method for forming a silicon-on-plastic wafer
12/27/2007US20070298587 Method of separating layers of material
12/27/2007US20070298586 Method of manufacturing semiconductor device
12/27/2007US20070298585 Dielectric deposition and etch back processes for bottom up gapfill
12/27/2007US20070298584 Method for fabricating semiconductor device
12/27/2007US20070298583 Method for forming a shallow trench isolation region
12/27/2007US20070298582 Method of performing a double-sided process
12/27/2007US20070298581 Method of manufacturing suspension structure and chamber
12/27/2007US20070298580 Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricating
12/27/2007US20070298579 Methods of employing a thin oxide mask for high dose implants
12/27/2007US20070298578 Bipolar transistor with dual shallow trench isolation and low base resistance
12/27/2007US20070298577 Method for manufacturing semiconductor device
12/27/2007US20070298576 Methods of forming bipolar transistors by silicide through contact and structures formed thereby
12/27/2007US20070298575 Methods for contact resistance reduction of advanced cmos devices
12/27/2007US20070298574 Method of fabricating different semiconductor device types with reduced sets of pattern levels
12/27/2007US20070298573 Semiconductor device and method for manufacturing the same
12/27/2007US20070298572 FIELD EFFECT TRANSISTORS (FETs) WITH MULTIPLE AND/OR STAIRCASE SILICIDE
12/27/2007US20070298571 Single chip data processing device with embedded nonvolatile memory and method thereof
12/27/2007US20070298570 Methods of Forming Integrated Circuitry, Methods of Forming Memory Circuitry, and Methods of Forming Field Effect Transistors
12/27/2007US20070298569 Non-volatile memory having three states and method for manufacturing the same
12/27/2007US20070298568 Scaled dielectric enabled by stack sidewall process
12/27/2007US20070298567 Sram cell structure and manufacturing method thereof
12/27/2007US20070298566 Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance
12/27/2007US20070298565 Junction leakage reduction in SiGe process by implantation
12/27/2007US20070298564 Vertical Field-Effect Transistor and Method of Forming the Same
12/27/2007US20070298563 Method of manufacturing a semiconductor integrated circuit device
12/27/2007US20070298562 Method of manufacturing a semiconductor integrated circuit device
12/27/2007US20070298561 INTEGRATED SiGe NMOS AND PMOS TRANSISTORS
12/27/2007US20070298560 Semiconductor Device
12/27/2007US20070298559 Vertical Field-Effect Transistor and Method of Forming the Same
12/27/2007US20070298558 Method of fabricating semiconductor device and semiconductor device
12/27/2007US20070298557 Junction leakage reduction in SiGe process by tilt implantation
12/27/2007US20070298556 Field effect transistor with enhanced insulator structure
12/27/2007US20070298555 Method of manufacturing a semiconductor device
12/27/2007US20070298554 Tft lcd array substrate and manufacturing method thereof
12/27/2007US20070298553 Thin Film Transistor and Method For Production Thereof
12/27/2007US20070298552 High performance 3d fet structures, and methods for forming the same using preferential crystallographic etching
12/27/2007US20070298551 Fabrication of silicon nano wires and gate-all-around MOS devices
12/27/2007US20070298550 Method for making thin-film semiconductor device
12/27/2007US20070298549 Method of fabricating a strained multi-gate transistor and devices obtained thereof
12/27/2007US20070298548 Active matrix display
12/27/2007US20070298547 Semiconductor device having a composite passivation layer and method of manufacturing the same
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