Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
01/2008
01/29/2008US7323729 Methods for improving quality of high temperature oxide (HTO) formed from halogen-containing precursor and products thereof and apparatus therefor
01/29/2008US7323727 System with meshed power and signal buses on cell array
01/29/2008US7323724 Nitride semiconductor device
01/29/2008US7323719 Group III-V nitride series semiconductor substrate and assessment method therefor
01/29/2008US7323717 Semiconductor device
01/29/2008US7323716 Manufacturing method of thin film transistor substrate
01/29/2008US7323715 Semiconductor device and manufacturing method thereof
01/29/2008US7323712 Anisotropically conductive connector and production process thereof, and probe member
01/29/2008US7323710 Fin field effect transistors having multi-layer fin patterns
01/29/2008US7323700 Method and system for controlling beam scanning in an ion implantation device
01/29/2008US7323695 Reciprocating drive for scanning a workpiece
01/29/2008US7323685 Ion beam processing method
01/29/2008US7323684 Scanning probe microscope and specimen observation method and semiconductor device manufacturing method using said scanning probe microscope
01/29/2008US7323661 Heat treatment apparatus using a lamp for rapidly and uniformly heating a wafer
01/29/2008US7323522 Curing agents; curable, colorless; radiation transparent; discoloration inhibition
01/29/2008US7323426 High strain point glasses
01/29/2008US7323424 Semiconductor constructions comprising cerium oxide and titanium oxide
01/29/2008US7323423 Forming high-k dielectric layers on smooth substrates
01/29/2008US7323422 Dielectric layers and methods of forming the same
01/29/2008US7323421 Silicon wafer etching process and composition
01/29/2008US7323420 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device
01/29/2008US7323418 Etch-back process for capping a polymer memory device
01/29/2008US7323417 Method of forming a recessed structure employing a reverse tone process
01/29/2008US7323416 Method and composition for polishing a substrate
01/29/2008US7323415 Polishing pad for semiconductor wafer, polishing multilayered body for semiconductor wafer having same, and method for polishing semiconductor wafer
01/29/2008US7323414 Method for polishing a substrate surface
01/29/2008US7323413 Method for stripping silicon nitride
01/29/2008US7323412 Atomic layer deposition methods, and methods of forming materials over semiconductor substrates
01/29/2008US7323411 Method of selective tungsten deposition on a silicon surface
01/29/2008US7323410 Dry etchback of interconnect contacts
01/29/2008US7323409 Method for forming a void free via
01/29/2008US7323408 Metal barrier cap fabrication by polymer lift-off
01/29/2008US7323407 Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material
01/29/2008US7323406 Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures
01/29/2008US7323405 Fine pitch low cost flip chip substrate
01/29/2008US7323404 Field effect transistor and method of manufacturing the same
01/29/2008US7323403 Multi-step process for patterning a metal gate electrode
01/29/2008US7323402 Trench Schottky barrier diode with differential oxide thickness
01/29/2008US7323401 Semiconductor substrate process using a low temperature deposited carbon-containing hard mask
01/29/2008US7323399 Clean process for an electron beam source
01/29/2008US7323398 Method of layer transfer comprising sequential implantations of atomic species
01/29/2008US7323397 Method and apparatus of fabricating a semiconductor device by back grinding and dicing
01/29/2008US7323396 Signal and/or ground planes with double buried insulator layers and fabrication process
01/29/2008US7323395 Manufacture of solid state electronic components
01/29/2008US7323394 Method of producing element separation structure
01/29/2008US7323393 Method of reducing film stress on overlay mark
01/29/2008US7323392 High performance transistor with a highly stressed channel
01/29/2008US7323391 Substrate having silicon germanium material and stressed silicon nitride layer
01/29/2008US7323390 Semiconductor device and method for production thereof
01/29/2008US7323389 Method of forming a FINFET structure
01/29/2008US7323388 SONOS memory cells and arrays and method of forming the same
01/29/2008US7323387 Method to make nano structure below 25 nanometer with high uniformity on large scale
01/29/2008US7323386 Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics
01/29/2008US7323385 Method of fabricating flash memory device
01/29/2008US7323384 Method of manufacturing semiconductor device
01/29/2008US7323383 Method for fabricating an NROM memory cell arrangement
01/29/2008US7323382 Intralevel decoupling capacitor, method of manufacture and testing circuit of the same
01/29/2008US7323381 Semiconductor device and manufacturing method thereof
01/29/2008US7323380 Single transistor vertical memory gain cell
01/29/2008US7323379 Fabrication process for increased capacitance in an embedded DRAM memory
01/29/2008US7323378 Method for fabricating CMOS image sensor
01/29/2008US7323377 Increasing self-aligned contact areas in integrated circuits using a disposable spacer
01/29/2008US7323376 Method for fabricating a semiconductor device including a group III nitride semiconductor
01/29/2008US7323375 Fin field effect transistor device and method of fabricating the same
01/29/2008US7323374 Dense chevron finFET and method of manufacturing same
01/29/2008US7323373 Method of forming a semiconductor device with decreased undercutting of semiconductor material
01/29/2008US7323372 Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors
01/29/2008US7323371 Deposition method of insulating layers having low dielectric constant of semiconductor device, a thin film transistor substrate using the same and a method of manufacturing the same
01/29/2008US7323370 SOI device with reduced junction capacitance
01/29/2008US7323369 Fabrication method for thin film transistor array substrate
01/29/2008US7323368 Method for manufacturing semiconductor device and heat treatment method
01/29/2008US7323367 Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions
01/29/2008US7323366 Manufacturing method of a semiconductor device
01/29/2008US7323365 Semiconductor device manufacturing method and manufacturing apparatus
01/29/2008US7323364 Stacked module systems and method
01/29/2008US7323363 Contact load profile modification for a compression socketed CPU
01/29/2008US7323362 Manufacturing system and apparatus for balanced product flow with application to low-stress underfilling of flip-chip electronic devices
01/29/2008US7323361 Packaging system for semiconductor devices
01/29/2008US7323360 Electronic assemblies with filled no-flow underfill
01/29/2008US7323359 Mounting method for a semiconductor component
01/29/2008US7323358 Method and system for sizing a load plate
01/29/2008US7323357 Method for manufacturing a resistively switching memory cell and memory device based thereon
01/29/2008US7323356 Growing a base thin film on a single-crystal substrate; depositing amorphous or polycrystalline LnCuOX thin film to form laminate; and annealing film at 500 degrees C. or more in a vacuum environment; light-emitting diodes, semiconductor leasers, filed-effect transistors, hetero-bipolar transistors
01/29/2008US7323355 Method of forming a microelectronic device
01/29/2008US7323354 Method of manufacturing MEMS device
01/29/2008US7323353 Resonator for thermo optic device
01/29/2008US7323352 Process for making light waveguide element
01/29/2008US7323351 Thin film transistor device and method of manufacturing the same
01/29/2008US7323350 Method of fabricating thin film calibration features for electron/ion beam image based metrology
01/29/2008US7323349 Self-aligned cross point resistor memory array
01/29/2008US7323348 Superconducting integrated circuit and method for fabrication thereof
01/29/2008US7323292 Coating substrates with polysilanes, then exposing to radiation and etching to form patterns used for masking; electrical and electronic apparatus such as random access or flash memory
01/29/2008US7323291 Dual layer workpiece masking and manufacturing process
01/29/2008US7323287 Positive type resist composition and resist pattern formation method using same
01/29/2008US7323286 Exposure latitude and line-edge roughness
01/29/2008US7323284 Useful as chemically amplified photoresist suitable for lithography making use of ultraviolet radiation, x-rays, or charged corpuscular beams; integrated circuits; semiconductors
01/29/2008US7323277 Photomask
01/29/2008US7323276 Substrate for photomask, photomask blank and photomask
01/29/2008US7323257 Complex oxide having an oxygen octahedral structure containing Si and Ge formed by post-annealing the components in a pressurized atmosphere including oxygen or ozone; dielectric capacitors
01/29/2008US7323256 Uncut single crystal III-V nitride (optionally doped) having a large area of at least 15 cm2 on a face and a uniformly low dislocation density not exceeding 3x106 dislocations per cm2 of growth surface area on the face; wafers for microelectronic and opto-electronic devices