Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2008
11/27/2008WO2008142681A2 Method for producing microneedle structures employing one-sided processing
11/27/2008WO2008142206A1 Method for producing circuit boards comprising electronic, optical and functional features
11/27/2008WO2008142115A1 Device for coating a plurality of closest-packed substrates arranged on a susceptor
11/27/2008WO2008142093A1 Chemical-mechanical polishing composition comprising metal-organic framework materials
11/27/2008WO2008141359A1 Method of removing mems devices from a handle substrate
11/27/2008WO2008121657B1 A recipe-and-component control module and methods thereof
11/27/2008WO2008121445A3 Parallel fabrication of nanogaps and devices thereof
11/27/2008WO2008121254A3 High capacity pick and place process
11/27/2008WO2008121172A3 Electrode isolation method and nanowire-based device having isolated electrode pair
11/27/2008WO2008106397A3 Process method to optimize fully silicided gate (fusi) thru pai implant
11/27/2008WO2008103964A3 Using spectra to determine polishing endpoints
11/27/2008WO2008103705A3 Methods of forming transistor contacts and via openings
11/27/2008WO2008101714A3 High throughput sem tool
11/27/2008WO2008101713A3 High throughput sem tool
11/27/2008WO2008100146A3 Method and device for encapsulating electronic components using underpressure
11/27/2008WO2008082923A3 Methods and apparatus for wafer edge processing
11/27/2008WO2008073954B1 Wet photoresist stripping process and apparatus
11/27/2008WO2008038158B1 Formation of through-wafer electrical interconnections and other structures using an etch stop layer
11/27/2008WO2008021460A3 Catch-cup to diverter alignment leveling jig
11/27/2008WO2008021221A3 Low voltage transient voltage suppressor with reduced breakdown voltage
11/27/2008WO2007143476A3 Apparatus and method for single substrate processing
11/27/2008WO2007121450A3 Device and method for handling an object of interest using a directional adhesive structure
11/27/2008WO2007112058A3 Carbon precursors for use during silicon epitaxial firm formation
11/27/2008WO2007092657A3 Semiconductor device and method for incorporating a halogen in a dielectric
11/27/2008US20080295055 Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit
11/27/2008US20080294282 Use of logical lots in semiconductor substrate processing
11/27/2008US20080293340 Methods and apparatus for removal of films and flakes from the edge of both sides of a substrate using backing pads
11/27/2008US20080293332 Polishing pad and method of polishing
11/27/2008US20080293322 Light emitting device and manufacturing method thereof
11/27/2008US20080293259 METHOD OF FORMING METAL/HIGH-k GATE STACKS WITH HIGH MOBILITY
11/27/2008US20080293258 Crystallization apparatus and crystallization method
11/27/2008US20080293257 Dual liner capping layer interconnect structure
11/27/2008US20080293256 Method for forming bismuth titanium silicon oxide thin film
11/27/2008US20080293255 Radical oxidation process for fabricating a nonvolatile charge trap memory device
11/27/2008US20080293254 Single-wafer process for fabricating a nonvolatile charge trap memory device
11/27/2008US20080293253 Wet etching of the edge and bevel of a silicon wafer
11/27/2008US20080293252 Resist removing method and resist removing apparatus
11/27/2008US20080293251 Method for manufacturing semiconductor device
11/27/2008US20080293250 Deep anisotropic silicon etch method
11/27/2008US20080293249 In-situ photoresist strip during plasma etching of active hard mask
11/27/2008US20080293248 Method of forming amorphous carbon film and method of manufacturing semiconductor device using the same
11/27/2008US20080293247 Semiconductor device and method of manufacturing the same
11/27/2008US20080293246 Vertical fet with nanowire channels and a silicided bottom contact
11/27/2008US20080293245 Semiconductor device and manufacturing method thereof
11/27/2008US20080293244 Methods of Positioning and/or Orienting Nanostructures
11/27/2008US20080293243 Prevention and Control of Intermetallic Alloy Inclusions
11/27/2008US20080293242 Metal spacer in single and dual damascene processing
11/27/2008US20080293241 Contact structures of wirings and methods for manufacturing the same, and thin film transistor array panels including the same and methods for manufacturing the same
11/27/2008US20080293240 Manufacturing method of a silicon carbide semiconductor device
11/27/2008US20080293239 Interconnect substrate, semiconductor device, methods of manufacturing the same, circuit board, and electronic equipment
11/27/2008US20080293238 Semiconductor device and method for fabricating the same
11/27/2008US20080293237 Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole
11/27/2008US20080293236 Method of manufacturing chip integrated substrate
11/27/2008US20080293235 Compound wirebonding and method for minimizing integrated circuit damage
11/27/2008US20080293234 Semiconductor device and manufacturing method of the same
11/27/2008US20080293233 Post last wiring level inductor using patterned plate process
11/27/2008US20080293232 Standoff Height Improvement for Bumping Technology Using Solder Resist
11/27/2008US20080293231 Method for forming electrode for Group-III nitride compound semiconductor light-emitting devices
11/27/2008US20080293230 Method of manufacturing a semiconductor device
11/27/2008US20080293229 Semiconductor device and manufacturing method of the same
11/27/2008US20080293228 CMOS Compatible Method of Forming Source/Drain Contacts for Self-Aligned Nanotube Devices
11/27/2008US20080293227 Method for forming gate electrode of semiconductor device
11/27/2008US20080293226 Semiconductor device and manufacturing method therefor
11/27/2008US20080293225 Method for manufacturing semiconductor device
11/27/2008US20080293224 Method of forming a diode and method of manufacturing a phase-change memory device using the same
11/27/2008US20080293223 Method for Manufacturing Strained Silicon
11/27/2008US20080293222 Method for forming silicon-germanium epitaxial layer
11/27/2008US20080293221 Method for holding semiconductor wafer
11/27/2008US20080293220 Wafer dividing method
11/27/2008US20080293219 Semiconductor wafer, semiconductor chip and dicing method of a semiconductor wafer
11/27/2008US20080293218 Wafer dividing method
11/27/2008US20080293217 Semiconductor substrates having useful and transfer layers
11/27/2008US20080293216 Method of manufacturing an inkjet head through the anodic bonding of silicon members
11/27/2008US20080293215 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions
11/27/2008US20080293214 Method of fabricating trench-constrained isolation diffusion for semiconductor devices
11/27/2008US20080293213 Method for preparing a shallow trench isolation
11/27/2008US20080293212 Method for forming storage node of capacitor in semiconductor device
11/27/2008US20080293211 High voltage deep trench capacitor
11/27/2008US20080293210 Post last wiring level inductor using patterned plate process
11/27/2008US20080293209 Thin film multiplayer ceramic capacitor devices and manufacture thereof
11/27/2008US20080293208 Method of fabricating oxide semiconductor device
11/27/2008US20080293207 Integration of non-volatile charge trap memory devices and logic cmos devices
11/27/2008US20080293206 Unique ldmos process integration
11/27/2008US20080293205 Method of forming metal silicide layer, and method of manufacturing semiconductor device using the same
11/27/2008US20080293204 Shallow junction formation and high dopant activation rate of MOS devices
11/27/2008US20080293203 Semiconductor device having a fin structure and method of manufacturing the same
11/27/2008US20080293202 Method for manufacturing semiconductor device
11/27/2008US20080293201 Nonvolatile semiconductor memory and a fabrication method thereof
11/27/2008US20080293200 Method of fabricating nonvolatile semiconductor memory device
11/27/2008US20080293199 Single-poly non-volatile memory device and its operation method
11/27/2008US20080293198 Method for manufacturing semiconductor device including etching process of silicon nitride film
11/27/2008US20080293197 Method of manufacturing semiconductor memory device
11/27/2008US20080293196 Method for fabricating multi-resistive state memory devices
11/27/2008US20080293195 Gate straining in a semiconductor device
11/27/2008US20080293194 Method of making a P-type metal-oxide semiconductor transistor and method of making a complementary metal-oxide semiconductor transistor
11/27/2008US20080293193 Use of low temperature anneal to provide low defect gate full silicidation
11/27/2008US20080293192 Semiconductor device with stressors and methods thereof
11/27/2008US20080293191 Semiconductor package
11/27/2008US20080293190 Semiconductor package, method for fabricating the same, and semiconductor device
11/27/2008US20080293189 Method of manufacturing chip integrated substrate
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