Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2009
04/14/2009US7518224 Offset integrated circuit package-on-package stacking system
04/14/2009US7518217 Semiconductor device, semiconductor wafer, chip size package, and methods of manufacturing and inspection therefor
04/14/2009US7518212 Graded GexSe100-x concentration in PCRAM
04/14/2009US7518210 Trench isolated integrated circuit devices including grooves
04/14/2009US7518208 Semiconductor device having power transistors and Schottky barrier diode
04/14/2009US7518205 Semiconductor package and method for manufacturing the same
04/14/2009US7518204 Semiconductor device
04/14/2009US7518201 Method for encapsulating an electrical component, and surface acoustic wave device encapsulated using said method
04/14/2009US7518198 Transistor and method for manufacturing the same
04/14/2009US7518195 Field-effect microelectronic device, capable of forming one or several transistor channels
04/14/2009US7518187 Soi wafer and a method for producing the same
04/14/2009US7518185 Semiconductor component and method of manufacturing
04/14/2009US7518184 DRAM access transistor
04/14/2009US7518183 Semiconductor device
04/14/2009US7518176 Programmable nonvolatile memory and semiconductor integrated circuit device
04/14/2009US7518175 Semiconductor memory device and method for fabricating the same
04/14/2009US7518174 Memory cell and method for forming the same
04/14/2009US7518167 Semiconductor device
04/14/2009US7518163 Gallium nitride-based compound semiconductor light-emitting device and negative electrode thereof
04/14/2009US7518159 Packaging technique for the fabrication of polarized light emitting diodes
04/14/2009US7518156 Semiconductor device
04/14/2009US7518154 Nitride semiconductor substrate and semiconductor element built thereon
04/14/2009US7518151 Gallium nitride/sapphire thin film having reduced bending deformation
04/14/2009US7518147 Organic electro luminescence device and fabrication method thereof
04/14/2009US7518144 Element for solid-state imaging device
04/14/2009US7518087 Laser processing apparatus and laser processing method
04/14/2009US7517818 Method for forming a nitrided germanium-containing layer using plasma processing
04/14/2009US7517817 Method for forming a silicon oxide layer using spin-on glass
04/14/2009US7517816 Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress
04/14/2009US7517815 Spin-on glass composition, method of preparing the spin-on glass composition and method of forming a porous silicon oxide layer using the spin-on glass composition
04/14/2009US7517814 Method and system for forming an oxynitride layer by performing oxidation and nitridation concurrently
04/14/2009US7517813 Two-step oxidation process for semiconductor wafers
04/14/2009US7517812 Method and system for forming a nitrided germanium-containing layer using plasma processing
04/14/2009US7517811 Method for fabricating a floating gate of flash rom
04/14/2009US7517810 Reduced metal design rules for power devices
04/14/2009US7517809 Removal of MEMS sacrificial layers using supercritical fluid/chemical formulations
04/14/2009US7517808 Method for forming and removing a patterned silicone film
04/14/2009US7517807 Methods for fabricating semiconductor structures
04/14/2009US7517806 Integrated circuit having pairs of parallel complementary FinFETs
04/14/2009US7517804 Selective etch chemistries for forming high aspect ratio features and associated structures
04/14/2009US7517803 Silicon parts having reduced metallic impurity concentration for plasma reaction chambers
04/14/2009US7517802 Method for reducing foreign material concentrations in etch chambers
04/14/2009US7517801 Method for selectivity control in a plasma processing system
04/14/2009US7517800 Chemical vapor deposition of a titanium nitride film from a titanium halide and ammonia at 300-450 degrees C; annealing; purging the ammonia; and repeating the steps at least once; supressed generation of irregularly grown objects in the film
04/14/2009US7517799 Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer
04/14/2009US7517798 Methods for forming through-wafer interconnects and structures resulting therefrom
04/14/2009US7517797 Carrier for wafer-scale package, wafer-scale package including the carrier, and methods
04/14/2009US7517796 Method for patterning submicron pillars
04/14/2009US7517795 Stabilization of Ni monosilicide thin films in CMOS devices using implantation of ions before silicidation
04/14/2009US7517794 Method for fabricating nanoscale features
04/14/2009US7517793 Method of forming metal wire in semiconductor device
04/14/2009US7517792 Semiconductor device having a multilayer interconnection structure, fabrication method thereof, and designing method thereof
04/14/2009US7517791 Method for manufacturing semiconductor device
04/14/2009US7517790 Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modification
04/14/2009US7517789 Solder bumps in flip-chip technologies
04/14/2009US7517788 System, apparatus, and method for advanced solder bumping
04/14/2009US7517786 Methods of forming wire bonds for semiconductor constructions
04/14/2009US7517785 Electronic interconnects and methods of making same
04/14/2009US7517784 Chemical vapor deposition with a dialkyl metal and NO alone or with an oxidizer; NO decomposition and atomic nitrogen incorporation into the formed transparent metal conducting oxide; without co-doping, plasma enhancement or the use of high temperature
04/14/2009US7517783 Molybdenum-doped indium oxide structures and methods
04/14/2009US7517782 Method of forming a metal layer over a patterned dielectric by wet chemical deposition including an electroless and a powered phase
04/14/2009US7517781 Method of manufacturing semiconductor device
04/14/2009US7517780 Method for eliminating polycide voids through nitrogen implantation
04/14/2009US7517779 Recessed drain extensions in transistor device
04/14/2009US7517778 Structure of high performance combo chip and processing method
04/14/2009US7517777 Method of manufacturing semiconductor device and semiconductor device formed by the method
04/14/2009US7517776 Method for controlling dislocation positions in silicon germanium buffer layers
04/14/2009US7517775 Methods of selective deposition of heavily doped epitaxial SiGe
04/14/2009US7517774 Laser annealing method
04/14/2009US7517773 Method of manufacturing a thin film transistor
04/14/2009US7517772 Selective etch for patterning a semiconductor film deposited non-selectively
04/14/2009US7517771 Method for manufacturing semiconductor device having trench
04/14/2009US7517770 Method for forming metal line and semiconductor device including the same
04/14/2009US7517769 Integrateable capacitors and microcoils and methods of making thereof
04/14/2009US7517768 Method for fabricating a heterojunction bipolar transistor
04/14/2009US7517767 Forming conductive stud for semiconductive devices
04/14/2009US7517766 Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device
04/14/2009US7517765 Method for forming germanides and devices obtained thereof
04/14/2009US7517764 Bulk FinFET device
04/14/2009US7517763 Semiconductor device having fuse and capacitor at the same level and method of fabricating the same
04/14/2009US7517762 Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area
04/14/2009US7517761 Method for manufacturing semiconductor device
04/14/2009US7517760 Semiconductor device manufacturing method including three gate insulating films
04/14/2009US7517759 Method of fabricating metal oxide semiconductor device
04/14/2009US7517758 Method of forming a vertical transistor
04/14/2009US7517757 Non-volatile memory device having dual gate and method of forming the same
04/14/2009US7517756 Flash memory array with increased coupling between floating and control gates
04/14/2009US7517755 Method for fabricating semiconductor device
04/14/2009US7517754 Methods of forming semiconductor constructions
04/14/2009US7517753 Methods of forming pluralities of capacitors
04/14/2009US7517752 Method of fabricating semiconductor device having storage capacitor and higher voltage resistance capacitor and semiconductor device fabricated using the same
04/14/2009US7517751 Substrate treating method
04/14/2009US7517750 Flash memory devices having multilayered inter-gate dielectric layers including metal oxide layers and methods of manufacturing the same
04/14/2009US7517749 Method for forming an array with polysilicon local interconnects
04/14/2009US7517748 Method of fabricating trench-constrained isolation diffusion for semiconductor devices
04/14/2009US7517747 Nanocrystal non-volatile memory cell and method therefor
04/14/2009US7517746 Metal oxide semiconductor transistor with Y shape metal gate and fabricating method thereof
04/14/2009US7517745 Semiconductor device having MOSFET with offset-spacer, and manufacturing method thereof
04/14/2009US7517744 Capacitorless DRAM on bulk silicon
04/14/2009US7517743 Fully-depleted (FD) (SOI) MOSFET access transistor and method of fabrication