| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 04/16/2009 | WO2009026240A8 Methods for liquid transfer coating of three-dimensional substrates |
| 04/16/2009 | WO2009023785A3 Static random access memory cell testing and biasing |
| 04/16/2009 | WO2009023675A3 Improved metal conservation with stripper solutions containing resorcinol |
| 04/16/2009 | WO2009023061A3 Dielectrics using substantially longitudinally oriented insulated conductive wires |
| 04/16/2009 | WO2009017835A3 Semiconductor packaging process using through silicon vias |
| 04/16/2009 | WO2009017782A3 Ruthenium cmp compositions and methods |
| 04/16/2009 | WO2009016304A3 Method for coating two elements hybridized by means of a soldering material |
| 04/16/2009 | WO2009012469A3 Structures of and methods for forming vertically aligned si wire arrays |
| 04/16/2009 | WO2009008958A3 Method of post etch polymer residue removal |
| 04/16/2009 | WO2008137459A3 Agitation of electrolytic solution in electrodeposition |
| 04/16/2009 | WO2008132734A9 Focused ion beam deep nano- patterning method |
| 04/16/2009 | WO2008127220A3 Methods for in-situ generation of reactive etch and growth specie in film formation processes |
| 04/16/2009 | WO2008118193A3 Wafer-level interconnect for high mechanical reliability applications |
| 04/16/2009 | WO2008097877A3 Heteroelement siloxane compounds and polymers |
| 04/16/2009 | WO2008067537A3 Method and apparatus for growth of iii-nitride semiconductor epitaxial layers |
| 04/16/2009 | WO2008060293A3 Preparation of nano-tubular titania substrates having gold and carbon particles deposited thereon and their use in photo-electrolysis of water |
| 04/16/2009 | WO2008031255A8 Method of self-aligned silicon nitride overlying for the borderless contact hole of copper technology |
| 04/16/2009 | WO2008027196A9 Dynamic surface annealing of implanted dopants with low temperature hdpcvd process for depositing a high extinction coefficient optical absorber layer |
| 04/16/2009 | WO2008021646A3 Eeprom memory array having 5f2 cells |
| 04/16/2009 | WO2007120466A3 Methods of reducing the bandgap energy of a metal oxide |
| 04/16/2009 | WO2007106101A3 Process for making contained layers and devices made with same |
| 04/16/2009 | WO2007061509A3 Modular diode laser assembly |
| 04/16/2009 | WO2007046852A3 Discretized processing and process sequence integration of substrate regions |
| 04/16/2009 | WO2007044447A3 Composition and method for selectively etching gate spacer oxide material |
| 04/16/2009 | WO2007041029A3 Sram cell with asymmetrical transistors for reduced leakage |
| 04/16/2009 | WO2007040992A3 Microelectronic assembly and method for forming the same |
| 04/16/2009 | WO2007040991A3 Magnetic tunnel junction temperature sensors and methods |
| 04/16/2009 | WO2007040749A3 A method of forming a silicon oxynitride film with tensile stress |
| 04/16/2009 | WO2007040688A3 Cmos process for fabrication of ultra small or non standard size or shape semiconductor die |
| 04/16/2009 | WO2007040668A3 Stacked contact bump |
| 04/16/2009 | WO2007028136A3 Protective barrier layer for semiconductor device electrodes |
| 04/16/2009 | WO2007027169A3 Method of manufacturing silicon topological capacitors |
| 04/16/2009 | WO2007025259A3 MOBILITY ENHANCEMENT IN SiGe HETEROJUNCTION BIPOLAR TRANSISTORS |
| 04/16/2009 | WO2007024760A3 Machine vision counting system apparatus and method |
| 04/16/2009 | WO2007024730A3 Wafer level hermetic bond using metal alloy |
| 04/16/2009 | WO2007005228A3 Hermetic seals for micro-electromechanical system devices |
| 04/16/2009 | WO2007005190A3 Source side injection storage device and method therefor |
| 04/16/2009 | WO2007002244A3 High temperature packaging for electronic components, modules and assemblies |
| 04/16/2009 | WO2007001782A3 Tunable antifuse element and method of manufacture |
| 04/16/2009 | WO2007001357A3 System and method for controlling nanostructure growth |
| 04/16/2009 | WO2006135682A3 Wafer level bumpless method of making a flip chip mounted semiconductor device package |
| 04/16/2009 | WO2006133249A3 Integrated chemical mechanical polishing composition and process for single platen processing |
| 04/16/2009 | WO2006130558A3 Flexible structures for sensors and electronics |
| 04/16/2009 | WO2006130319A3 Critical dimension reduction and roughness control |
| 04/16/2009 | WO2006127696A3 Process for fabricating an integrated circuit package |
| 04/16/2009 | WO2006124966A3 Low temperature absorption layer deposition and high speed optical annealing system |
| 04/16/2009 | WO2006124131A3 Substrates including a capping layer on electrically conductive regions |
| 04/16/2009 | WO2006118657A3 Schottky device and method of forming |
| 04/16/2009 | WO2006116337A3 Doped semiconductor nanocrystals and methods of making same |
| 04/16/2009 | WO2006113609A3 Maskless multiple sheet polysilicon resistor |
| 04/16/2009 | WO2006113442A3 Wafer separation technique for the fabrication of free-standing (al, in, ga)n wafers |
| 04/16/2009 | WO2006107422A3 Method of making a substrate structure with enhanced surface area |
| 04/16/2009 | WO2006088697A3 Methods of making gas distribution members for plasma processing apparatuses |
| 04/16/2009 | WO2006084250A3 A subthreshold design methodology for ultra-low power systems |
| 04/16/2009 | WO2006081290A3 Apparatus for electroless deposition of metals onto semiconductor substrates |
| 04/16/2009 | WO2006081233A3 Confinement ring drive |
| 04/16/2009 | WO2006078585A3 Wafer support pin assembly |
| 04/16/2009 | WO2006055200A3 Field effect transistor having a carrier exclusion layer |
| 04/16/2009 | WO2006053055A3 High-voltage transistor fabrication with trench etching technique |
| 04/16/2009 | WO2006028779A3 Electrically floating diagnostic plasma probe with ion property sensors |
| 04/16/2009 | WO2006023835A3 Stacked wafer scale package |
| 04/16/2009 | WO2006014612A3 Method of controlling the film properties of a cvd-deposited silicon nitride film |
| 04/16/2009 | WO2006011954A3 Diagnostic plasma measurement device having patterned sensors and features |
| 04/16/2009 | WO2005122286A3 Selective implementation of barrier layers to achieve threshold voltage control in cmos device fabrication with high k dielectrics |
| 04/16/2009 | WO2005084221A3 Self aligned contact structure for trench device |
| 04/16/2009 | WO2005050257A3 High temperature imaging device |
| 04/16/2009 | US20090099991 Method and system for predicting process performance using material processing tool and sensor data |
| 04/16/2009 | US20090099819 Diagnostic method for root-cause analysis of fet performance variation |
| 04/16/2009 | US20090099681 Method for creating wafer batches in an automated batch process tool |
| 04/16/2009 | US20090099051 Aqueous fluoride compositions for cleaning semiconductor devices |
| 04/16/2009 | US20090098808 Grinding method for wafer |
| 04/16/2009 | US20090098742 System and Process for Heating Semiconductor Wafers by Optimizing Absorption of Electromagnetic Energy |
| 04/16/2009 | US20090098741 Method for forming ultra-thin boron-containing nitride films and related apparatus |
| 04/16/2009 | US20090098740 Method of forming isolation layer in semiconductor device |
| 04/16/2009 | US20090098739 Method for manufacturing soi substrate |
| 04/16/2009 | US20090098738 Method of fabricating semiconductor device |
| 04/16/2009 | US20090098737 Method of patterning multilayer metal gate structures for cmos devices |
| 04/16/2009 | US20090098736 Dry-etching method |
| 04/16/2009 | US20090098735 Method of forming isolation layer in semicondcutor device |
| 04/16/2009 | US20090098734 Method of forming shallow trench isolation structure and method of polishing semiconductor structure |
| 04/16/2009 | US20090098733 Method of forming metal layer used in the fabrication of semiconductor device |
| 04/16/2009 | US20090098732 Semiconductor device and method of forming contact plug of semiconductor device |
| 04/16/2009 | US20090098731 Methods for Forming a Through Via |
| 04/16/2009 | US20090098730 Semiconductor device and method of fabricating the same |
| 04/16/2009 | US20090098729 Method for manufacturing a semiconductor device |
| 04/16/2009 | US20090098728 Structure cu liner for interconnects using a double-bilayer processing scheme |
| 04/16/2009 | US20090098727 Method of Forming Metal Line of Semiconductor Device |
| 04/16/2009 | US20090098726 Method for forming inlaid interconnect |
| 04/16/2009 | US20090098724 Method Of Forming Metallic Bump And Seal For Semiconductor Device |
| 04/16/2009 | US20090098723 Method Of Forming Metallic Bump On I/O Pad |
| 04/16/2009 | US20090098722 Method of forming a semiconductor memory device |
| 04/16/2009 | US20090098721 Method of fabricating a flash memory |
| 04/16/2009 | US20090098720 Semiconductor device and method for manufacturing the same |
| 04/16/2009 | US20090098719 Method for manufacturing silicon carbide semiconductor device |
| 04/16/2009 | US20090098718 Multiple mask and method for producing differently doped regions |
| 04/16/2009 | US20090098716 Method for making a self-converged memory material element for memory cell |
| 04/16/2009 | US20090098715 Process for manufacturing silicon wafers for solar cell |
| 04/16/2009 | US20090098714 Method for forming III-nitrides semiconductor epilayer on the semiconductor substrate |
| 04/16/2009 | US20090098713 Object cutting method |
| 04/16/2009 | US20090098712 Substrate dividing method |