Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
08/2009
08/20/2009US20090207649 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
08/20/2009US20090207645 Method and apparatus for accessing a bidirectional memory
08/20/2009US20090207642 Semiconductor signal processing device
08/19/2009EP1938331A4 Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers
08/19/2009CN101512660A Detecting radiation-based attacks
08/19/2009CN100530420C Non-volatile passive matrix and method for read out of the same
08/19/2009CN100530418C Multi-port memory based on DRAM core
08/19/2009CN100530417C Multi-port memory based on DRAM core
08/19/2009CN100530414C Method and device for multibank memory scheduling
08/18/2009US7577058 Semiconductor device having input detection circuit which operates in a synchronous operation and an asynchronous operation
08/18/2009US7577057 Circuit and method for generating write data mask signal in synchronous semiconductor memory device
08/18/2009US7577056 System and method for using a DLL for signal timing control in a eDRAM
08/18/2009US7577055 Error detection on programmable logic resources
08/18/2009US7577054 Memory with word-line driver circuit having leakage prevention transistor
08/18/2009US7577046 Circuit and method for generating column path control signals in semiconductor device
08/18/2009US7577015 Memory content inverting to minimize NTBI effects
08/18/2009US7577011 Optimization of ROM structure by splitting
08/18/2009US7576469 Sensor comprising a surface wave component
08/18/2009CA2374506C Card memory apparatus
08/13/2009WO2009100108A1 System and method for decoding a memory array comprising blocks and sub-blocks
08/13/2009WO2009099821A1 Memory rank select using a glo'bal select pin
08/13/2009WO2009097693A1 Selective broadcasting of data in series connected devices
08/13/2009WO2009097677A1 Non-volatile memory device having configurable page size
08/13/2009US20090204780 Data storage unit, data storage controlling apparatus and method, and data storage controlling program
08/13/2009US20090204747 Non binary flash array architecture and method of operation
08/13/2009US20090201758 Method for designing integrated circuit incorporating memory macro
08/13/2009US20090201753 Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address
08/13/2009US20090201752 Semiconductor memory device
08/13/2009US20090201751 Semiconductor device in which a memory array is refreshed based on an address signal
08/13/2009US20090201738 Semiconductor memory device
08/13/2009US20090201733 Flash memory device
08/12/2009EP1661137B1 Low voltage operation dram control circuits
08/12/2009CN101506897A Dual data-dependent busses for coupling read/write circuits to a memory array
08/12/2009CN101506896A Method and apparatus for memory array incorporating two data busses for memory array block selection
08/12/2009CN101506895A Scalable memory system
08/11/2009US7573939 Memory cell circuit, memory device, motion vector detection device, and motion compensation prediction coding device
08/11/2009US7573779 Semiconductor memory and electronic device
08/11/2009US7573778 Semiconductor memory device
08/11/2009US7573777 Over driver control signal generator in semiconductor memory device
08/11/2009US7573776 Semiconductor memory device having data-compress test mode
08/06/2009US20090196118 Design Structure Of Implementing Power Savings During Addressing Of DRAM Architectures
08/06/2009US20090196117 System and method for memory array decoding
08/06/2009US20090196116 Semiconductor memory having a bank with sub-banks
08/06/2009US20090196115 Semiconductor device for preventing erroneous write to memory cell in switching operational mode between normal mode and standby mode
08/06/2009US20090196114 Semiconductor storage device
08/06/2009US20090196112 Block decoding circuits of semiconductor memory devices and methods of operating the same
08/06/2009US20090196109 Rank select using a global select pin
08/06/2009US20090196108 Semiconductor memory device and semiconductor memory device test method
08/06/2009US20090196103 Non-volatile memory device having configurable page size
08/06/2009US20090196102 Flexible memory operations in nand flash devices
08/06/2009US20090196101 Memory module
08/06/2009US20090196084 Memory chip array
08/06/2009US20090196083 Integrated circuits to control access to multiple layers of memory
08/06/2009US20090195281 Timing Signal Generating Circuit, Semiconductor Integrated Circuit Device and Semiconductor Integrated Circuit System to which the Timing Signal Generating Circuit is Applied, and Signal Transmission System
08/05/2009EP2016588A4 Dynamic random access memory with fully independent partial array refresh function
08/05/2009EP1989711A4 Method and apparatus for cascade memory
08/05/2009EP1913597A4 Memory device and method having multiple address, data and command buses
08/05/2009EP0870241B2 Protocol for communication with dynamic memory
08/05/2009CN100524525C Semiconductor integrated circuit device including OPT memory, and method of programming OPT memory
08/05/2009CN100524514C Efficient register for additive latency in DDR2 mode of operation
08/05/2009CN100524513C Multi-port memory device with global data bus connection circuit
08/05/2009CN100524504C Temperature-compensated bias generator circuit and method for generating bias in a memory device
08/05/2009CN100524248C Nonvolatile memory system and management method for nonvolatile memory
08/04/2009US7571260 CPU address decoding with multiple target resources
08/04/2009US7570542 Circuit and method for generating data output control signal for semiconductor integrated circuit
08/04/2009US7570541 Semiconductor memory device
08/04/2009US7570540 Multiport semiconductor memory device
08/04/2009US7570539 Method for identifying memory bit cells and connections
08/04/2009US7570538 Method for writing to multiple banks of a memory device
08/04/2009US7570535 Semiconductor integrated circuit device having memory macros and logic cores on board
08/04/2009US7570504 Device and method to reduce wordline RC time constant in semiconductor memory devices
08/04/2009US7570078 Programmable logic device providing serial peripheral interfaces
08/04/2009US7569880 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
07/2009
07/30/2009US20090190432 DRAM with Page Access
07/30/2009US20090190431 Double data rate-single data rate input block and method for using same
07/30/2009US20090190430 Non-volatile latch circuit for restoring data after power interruption
07/30/2009US20090190429 System to Provide Memory System Power Reduction Without Reducing Overall Memory System Performance
07/30/2009US20090190420 Delay locked loop with frequency control
07/30/2009US20090190418 Semiconductor memory, method of controlling the semiconductor memory, and memory system
07/30/2009US20090190417 Semiconductor integrated circuit device and method of testing same
07/30/2009US20090190416 Semiconductor storage device and method for producing semiconductor storage device
07/30/2009US20090190414 Semiconductor device
07/30/2009US20090190411 Semiconductor memory device and control method
07/30/2009US20090190405 Non-volatile semiconductor memory device
07/30/2009US20090190401 Memory device employing NVRAM and flash memory cells
07/30/2009US20090190391 Magnetoresistive random access memory
07/30/2009US20090190389 Multi-port sram with six-transistor memory cells
07/30/2009DE102008034346A1 Method for accessing memory chip in dual in-line memory module, involves inputting column address signals into input pins, respectively, where length of packets of respective signals corresponds to elementary periods of clock signals
07/29/2009EP2002443A4 Memory with clocked sense amplifier
07/29/2009CN100520974C Simutaneously read and write flash memory device having separately read/write logic row decoder circuitry
07/29/2009CN100520964C Semiconductor memory
07/29/2009CN100520961C Semiconductor memory device
07/29/2009CN100520955C Memory appts.
07/29/2009CN100520733C Data processing apparatus, and its processing method and mobile telephone apparatus
07/28/2009US7567484 Method of preventing dielectric breakdown of semiconductor device and semiconductor device preventing dielectric breakdown
07/28/2009US7567483 Semiconductor memory device and method for operating the same
07/28/2009US7567481 Semiconductor memory device adapted to communicate decoding signals in a word line direction
07/28/2009US7567480 Semiconductor memory device
07/28/2009US7567479 Integrated circuit device and electronic instrument
07/28/2009US7567478 Leakage optimized memory
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