Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
11/2009
11/26/2009US20090290419 Semiconductor memory device using only single-channel transistor to apply voltage to selected word line
11/26/2009US20090290415 Card controller controlling semiconductor memory including memory cell having charge accumulation layer and control gate
11/26/2009US20090290403 Semiconductor device
11/26/2009US20090290402 Semiconductor memory devices and methods of arranging memory cell arrays thereof
11/25/2009EP2122630A1 Mask programmable anti-fuse architecture
11/25/2009EP2122628A1 Source side asymmetrical precharge programming scheme
11/25/2009CN101587742A Semiconductor memory device and data input/output method thereof
11/25/2009CN101587741A Word-line tracking system
11/25/2009CN100562942C Semiconductor memory device
11/24/2009US7623408 Semiconductor memory device comprising data path controller and related method
11/24/2009US7623407 Semiconductor device
11/24/2009US7623406 Accessing semiconductor memory device according to an address and additional access information
11/24/2009US7623397 Semiconductor device
11/24/2009US7623394 High voltage generating device of semiconductor device
11/24/2009US7623382 Semiconductor memory and address-decoding circuit and method for decoding address
11/24/2009US7623381 Non-volatile memory device and method of erasing the same
11/24/2009US7622766 Semiconductor memory device and method for producing the same
11/19/2009US20090285048 Counter circuit, latency counter, semiconductor memory device including the same, and data processing system
11/19/2009US20090285047 Row decode driver gradient design in a memory device
11/19/2009US20090285042 Memory interface circuit and memory system including the same
11/19/2009US20090285035 Pipelined wordline memory architecture
11/19/2009US20090285034 Latency counter, semiconductor memory device including the same, and data processing system
11/19/2009US20090285031 System and method for simulating an aspect of a memory circuit
11/19/2009DE102008001739A1 Verfahren zum Steuern eines Zugriffs auf Bereiche eines Speichers aus mehreren Prozessen heraus und Kommunikations-Modul mit einem Nachrichten-Speicher zur Realisierung des Verfahrens A method for controlling access to areas of memory of a plurality of processes and out of communication module having a message memory for implementing the method
11/18/2009EP2118903A1 System and method of operating memory devices of mixed type
11/18/2009EP2118902A1 Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices
11/18/2009CN101582291A Semiconductor integrated circuit
11/18/2009CN101582290A Multi-port memory based on dram core and control method thereof
11/18/2009CN100561597C Semiconductor memory device and method of testing semiconductor memory device
11/18/2009CN100561596C Method for accessing semiconductor memory device and electronic information apparatus using same
11/18/2009CN100561591C Reconfigurable electronic device having interconnected data storage devices
11/18/2009CN100561458C Media diary application for use with digital device
11/12/2009US20090282318 Semiconductor memory device
11/12/2009US20090279378 Semiconductor memory device
11/12/2009US20090279377 Semiconductor memory device
11/12/2009US20090279372 Semiconductor memory device and sense amplifier
11/12/2009US20090279351 Semiconductor memory devices and methods having core structures for multi-writing
11/12/2009US20090279348 Semiconductor memory device
11/12/2009US20090279344 Resistance change memory device
11/12/2009DE19952011B4 Adressentaktsignalgenerator für Speichergerät Address clock signal generator for storage device
11/12/2009DE19655409B4 Halbleiterspeichervorrichtung A semiconductor memory device
11/11/2009EP1800311B1 Multi-column addressing mode memory system including an intergrated circuit memory device
11/11/2009CN100559504C Integrated electronic components with the memory unit, its realization method, and semiconductor memory unit
11/11/2009CN100559501C Semiconductor storage device having effective and reliable redundancy process
11/10/2009US7616630 Semiconductor memory device
11/10/2009US7616521 Semiconductor memory device selectively enabling address buffer according to data output
11/10/2009US7616520 Integrated circuit device and electronic instrument
11/10/2009US7616519 Semiconductor integrated circuit device
11/10/2009US7616518 Multi-port memory device with serial input/output interface
11/05/2009US20090274002 Semiconductor integrated circuit and method of processing address and command signals thereof
11/05/2009US20090274001 Semiconductor memory device and method for operating the same
11/05/2009US20090273996 Memory testing system and memory module thereof
11/05/2009US20090273991 Semiconductor memory device, operating method thereof, and compression test method thereof
11/05/2009US20090273990 Semiconductor device
11/05/2009US20090273989 Synchronous Command Base Write Recovery Time Auto Precharge Control
11/05/2009US20090273985 Semiconductor device having multiple i/o modes
11/05/2009US20090273982 Semiconductor memory device, semiconductor device, and data write method
11/03/2009US7613868 Method and system for optimizing the number of word line segments in a segmented MRAM array
11/03/2009US7613070 Interleaved input signal path for multiplexed input
11/03/2009US7613069 Address latch circuit of semiconductor memory device
11/03/2009US7613068 Read operation for non-volatile storage with compensation for coupling
11/03/2009US7613067 Soft error robust static random access memory cells
11/03/2009US7613066 Integrated circuit device and electronic instrument
11/03/2009US7613065 Multi-port memory device
11/03/2009US7613050 Sense-amplifier assist (SAA) with power-reduction technique
11/03/2009US7613038 Semiconductor integrated circuit device
11/03/2009US7613026 Apparatus and methods for optically-coupled memory systems
11/03/2009US7613024 Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells
10/2009
10/29/2009WO2009131836A1 Systems and methods for dynamic power savings in electronic memory operation
10/29/2009US20090271499 Software and Method for Monitoring A Data Stream and for Capturing Desired Data Within the Data Stream
10/29/2009US20090268544 Memory device and method having programmable address configurations
10/29/2009US20090268543 Memory control circuit and memory accessing method
10/29/2009US20090268542 Semiconductor memory device
10/29/2009US20090268540 Systems and Methods for Dynamic Power Savings in Electronic Memory Operation
10/29/2009US20090268537 Semiconductor memory device
10/29/2009US20090268531 Semiconductor memory device with adjustable selected work line potential under low voltage condition
10/29/2009US20090268528 Semiconductor memory device and access method thereof
10/29/2009US20090268514 Semiconductor memory device and control method thereof
10/29/2009US20090268502 Semiconductor device with non-volatile memory and random access memory
10/29/2009US20090268499 Semiconductor memory device
10/29/2009CA2720069A1 Systems and methods for dynamic power savings in electronic memory operation
10/28/2009CN100555630C Delay locking loop of reinforced interfrence proof phase swinging of blocking circuit and its method
10/28/2009CN100555465C Memory system circuit for operating non-volatile memory system and method
10/27/2009US7610629 Access control apparatus, access control method, and access control program
10/27/2009US7610454 Address decoding method and related apparatus by comparing mutually exclusive bit-patterns of addresses
10/27/2009US7609584 Latency control circuit and method thereof and an auto-precharge control circuit and method thereof
10/27/2009US7609583 Selective edge phase mixing
10/27/2009US7609582 Branch target buffer and method of use
10/27/2009US7609566 Semiconductor memory device
10/27/2009US7609095 System and method for maintaining device operation during clock signal adjustments
10/22/2009US20090262596 Address decoder and/or access line driver and method for memory devices
10/22/2009US20090262595 Method and apparatus for operating maskable memory cells
10/22/2009US20090262592 Method and apparatus for synchronization of row and column access operations
10/22/2009US20090262591 Nand system with a data write frequency greater than a command-and-address-load frequency
10/22/2009US20090262590 Semiconductor memory device
10/22/2009US20090262589 Semiconductor memory device and method for operating the same
10/22/2009US20090262587 Semiconductor memory device
10/22/2009US20090262586 Semiconductor memory device voltage generating circuit for avoiding leakage currents of parasitic diodes
10/22/2009US20090262585 Input buffer and method with ac positive feedback, and a memory device and computer system using same
10/22/2009US20090262568 Semiconductor memory device
1 ... 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 ... 194