Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
03/2009
03/05/2009US20090059643 Semiconductor memory device
03/05/2009US20090059642 Memory Controller With Multi-Modal Reference Pad
03/05/2009US20090059640 Semiconductor device having multiport memory
03/05/2009US20090059639 Tree-style and-type match circuit device applied to content addressable memory
03/05/2009DE102008038877A1 Mehrportspeicherelement und Verfahren zum Zugreifen auf mehrere geteilte Speichereinheiten in einem Mehrportspeicherelement Multi-port memory element and method for accessing a plurality of divided storage units in a multi-port memory element
03/04/2009CN101377950A Routing access with minimized bus area in multi-port memory device
03/04/2009CN100466099C Semiconductor memory containing delay circuit capable of generating sufficiently stable delay signal
03/03/2009US7500213 Array-based architecture for molecular electronics
03/03/2009US7499372 Semiconductor memory device
03/03/2009US7499371 Semiconductor memory system with a variable and settable preamble f
03/03/2009US7499370 Synchronous semiconductor memory device
03/03/2009US7499369 Method of high-performance flash memory data transfer
03/03/2009US7499368 Variable clocking read capture for double data rate memory devices
03/03/2009US7499367 Semiconductor memory device having stacked bank structure
03/03/2009US7499366 Method for using dual data-dependent busses for coupling read/write circuits to a memory array
03/03/2009US7499365 Dual port PLD embedded memory block to support read-before-write in one clock cycle
03/03/2009US7499364 Multi-port semiconductor memory device and signal input/output method therefor
03/03/2009US7499363 Semiconductor memory apparatus capable of reducing ground noise
03/03/2009US7499356 Semiconductor memory device
03/03/2009US7499346 High voltage generating device of semiconductor device
03/03/2009US7499323 Flash memory device and data I/O operation method thereof
02/2009
02/26/2009WO2009026364A1 Threshold voltage digitizer for array of programmable threshold transistors
02/26/2009WO2008150844A4 Memory structure with word line buffers
02/26/2009US20090052271 Semiconductor memory device
02/26/2009US20090052270 Method of flexible memory segment assignment using a single chip select
02/26/2009US20090052269 Charge loss compensation methods and apparatus
02/26/2009US20090052268 System and method for providing temperature data from a memory device having a temperature sensor
02/26/2009US20090052267 Method of simple chip select for memory subsystems
02/26/2009US20090052264 Refresh characteristic testing circuit and method for testing refresh using the same
02/26/2009US20090052262 Semiconductor memory device
02/26/2009US20090052257 Nonvolatile semiconductor memories for preventing read disturbance and reading methods thereof
02/26/2009US20090052253 Memory device and method reducing fluctuation of read voltage generated during read while write operation
02/26/2009US20090052249 Semiconductor memory device having memory block configuration
02/26/2009US20090052240 Flash Memory Device and Method of Programming the Same
02/25/2009CN101375342A Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays
02/25/2009CN101375339A Method and apparatus for cascade memory
02/24/2009US7496781 Timing signal generating circuit with a master circuit and slave circuits
02/24/2009US7496728 Asynchronous jitter reduction technique
02/24/2009US7495993 Onboard data storage and method
02/24/2009US7495992 System for reducing wordline recovery time
02/24/2009US7495991 Memory chip architecture with high speed operation
02/24/2009US7495990 Semiconductor memory device and method of controlling the semiconductor memory device
02/24/2009US7495976 Repairing integrated circuit memory arrays
02/24/2009US7495974 Delay selecting circuit for semiconductor memory device
02/19/2009WO2009023024A1 Memory device with reduced buffer current during power-down mode
02/19/2009WO2009022024A1 Electronic system for emulating the chain of the dna structure of a chromosome
02/19/2009US20090046534 Method of Operating a Memory Apparatus, Memory Device and Memory Apparatus
02/19/2009US20090046533 Multichip system and method of transferring data therein
02/19/2009US20090046527 Auto precharge circuit sharing a write auto precharge signal generating unit
02/19/2009US20090046526 Word line driving circuit and method of testing a word line using the word line driving circuit
02/19/2009US20090046524 Multi-column decoder stress test circuit
02/19/2009US20090046522 Method for writing data in a non volatile memory unit
02/19/2009US20090046520 Semiconductor memory device having low power consumption type column decoder and read operation method thereof
02/19/2009US20090046517 Semiconductor device
02/19/2009DE102007036990A1 Verfahren zum Betrieb einer Speichervorrichtung, Speichereinrichtung und Speichervorrichtung A method of operating a memory device, storage device and storage device
02/19/2009DE102007036989A1 Verfahren zum Betrieb einer Speichervorrichtung, Speichereinrichtung und Speichervorrichtung A method of operating a memory device, storage device and storage device
02/18/2009EP1690260B1 Method for operating a data storage apparatus employing passive matrix addressing
02/17/2009US7492663 Storage device with protection against inadvertent writing
02/17/2009US7492662 Structure and method of implementing power savings during addressing of DRAM architectures
02/17/2009US7492661 Command generating circuit and semiconductor memory device having the same
02/17/2009US7492653 Semiconductor memory device capable of effectively testing failure of data
02/17/2009US7492648 Reducing leakage current in memory device using bitline isolation
02/17/2009US7492644 Semiconductor integrated circuit device
02/12/2009US20090043952 Moving sectors within a block of information in a flash memory mass storage architecture
02/12/2009US20090040861 Method of Operating a Memory Apparatus, Memory Device and Memory Apparatus
02/12/2009US20090040860 Semiconductor memory apparatus capable of selectively providing decoded row address
02/12/2009US20090040853 Method of precharging local input/output line and semiconductor memory device using the method
02/12/2009US20090040851 Semiconductor memory, test method of semiconductor memory and system
02/12/2009US20090040850 Semiconductor memory, test method of semiconductor memory and system
02/12/2009US20090040849 Semiconductor memory, test method of semiconductor memory and system
02/12/2009US20090040847 Output enable signal generating circuit and method of semiconductor memory apparatus
02/12/2009US20090040845 Column Path Circuit
02/12/2009US20090040844 Output control device
02/12/2009US20090040840 Semiconductor memory device and method of compensating for signal interference thereof
02/12/2009US20090040838 Delay locked operation in semiconductor memory device
02/12/2009US20090040830 Block decoder and semiconductor memory device including the same
02/12/2009US20090040827 Flash memory device for remapping bad blocks and bad block remapping method
02/12/2009US20090040819 Nonvolatile memory device using resistive elements and an associated driving method
02/12/2009US20090040159 Display driver, display device, and drive method
02/12/2009DE102007039762A1 Elektronische Schaltung und Verfahren zum Auswählen einer elektronischen Schaltung Electronic circuit and method for selecting an electronic circuit
02/12/2009DE102007039462A1 Verfahren und Vorrichtung zur Aufzählung Method and apparatus for enumeration
02/11/2009EP2022057A2 Sram split write control for a delay element
02/11/2009EP1055178B1 Data processor integrated circuit with a memory interface unit with programmable strobes to select different memory devices
02/11/2009CN101366090A System and method for low power wordline logic for a memory
02/11/2009CN101364436A Non-volatile memory and method for driving the same
02/11/2009CN100461294C Ferroelectric memory
02/10/2009US7489589 MRAM internal clock pulse generation with an ATD circuit and the method thereof
02/10/2009US7489587 Semiconductor memory device capable of controlling clock cycle time for reduced power consumption
02/10/2009US7489586 Semiconductor memory device and driving method thereof
02/10/2009US7489585 Global signal driver for individually adjusting driving strength of each memory bank
02/10/2009US7489584 High performance, low-leakage static random access memory (SRAM)
02/10/2009US7489583 Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays
02/10/2009US7489571 Semiconductor device for switching a defective memory cell bit of data to replacement data on the output data line
02/10/2009US7489539 Semiconductor memory device
02/10/2009US7489534 Semiconductor package for forming a double die package (DDP)
02/05/2009US20090034356 Dual-Port Memory
02/05/2009US20090034355 Integrated circuit including memory cells with tunnel fet as selection transistor
02/05/2009US20090034349 Semiconductor device
02/05/2009US20090034347 High speed dram architecture with uniform access latency
02/05/2009US20090034344 Methods and apparatus for strobe signaling and edge detection thereof
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