Patents
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Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
01/2009
01/06/2009US7474586 Random access memory (RAM) method of operation and device for search engine systems
01/06/2009US7474585 Memory with serial input-output terminals for address and data and method therefor
01/06/2009US7474578 Refresh control circuit and method thereof and bank address signal change circuit and methods thereof
01/06/2009US7474557 MRAM array and access method thereof
01/06/2009US7474553 Device writing to a plurality of rows in a memory matrix simultaneously
01/06/2009US7474550 Dynamic RAM-and semiconductor device
01/06/2009US7474299 Method for controlling a handheld computer by entering commands onto a displayed feature of the handheld computer
01/06/2009CA2357441C Support for exhaustion recovery in a data processing system with memory mirroring
01/01/2009US20090003122 Address synchronous circuit capable of reducing current consumption in dram
01/01/2009US20090003121 Column address control circuit capable of selectively enabling sense amplifier in response to column addresses
01/01/2009US20090003120 Power-saving semiconductor memory
01/01/2009US20090003119 Pseudo dual-port memory
01/01/2009US20090003118 Word line block select circuit with repair address decision unit
01/01/2009US20090003117 Semiconductor memory device
01/01/2009US20090003103 Semiconductor device and semiconductor memory tester
01/01/2009US20090003100 Semiconductor memory device and method of inputting addresses therein
01/01/2009US20090003097 Output control signal generating circuit
01/01/2009US20090003095 Column access control apparatus having fast column access speed at read operation
01/01/2009US20090003094 Semiconductor memory device having refresh mode and method for driving the same
01/01/2009US20090003087 Memory device bit line sensing system and method that compensates for bit line resistance variations
01/01/2009US20090003063 Method and device for demultiplexing a crossbar non-volatile memory
01/01/2009US20090003048 Nonvolatile memory device using a variable resistive element and associated operating method
01/01/2009US20090003040 Method and System For Encoding to Eliminate Parasitics in Crossbar Array Memories
01/01/2009US20090003026 Semiconductor memory device
12/2008
12/31/2008WO2009003115A1 Concurrent multiple-dimension word-addressable memory architecture
12/31/2008EP2008281A2 Multi-port memory device having variable port speeds
12/31/2008EP1905042A4 Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations
12/31/2008EP1747559B1 Method and apparatus for a dual power supply to embedded non-volatile memory
12/30/2008US7471590 Write control circuitry and method for a memory array configured with multiple memory subarrays
12/30/2008US7471584 Integrated semiconductor memory and method for operating an integrated semiconductor memory
12/30/2008US7471576 Method of transferring data in an electrically programmable memory
12/25/2008US20080316852 Nonvolatile semiconductor memory device
12/25/2008US20080316851 Semiconductor memory device
12/25/2008US20080316846 Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device
12/25/2008US20080316837 Semiconductor memory device capable of controlling potential level of power supply line and/or ground line
12/25/2008US20080316835 Concurrent Multiple-Dimension Word-Addressable Memory Architecture
12/25/2008US20080316834 Bias circuits and methods for enhanced reliability of flash memory device
12/25/2008US20080316825 Semiconductor memory device
12/25/2008US20080316819 Flash memory device capable of storing multi-bit data and single-bit data
12/25/2008US20080316798 Nonvolatile semiconductor memory device
12/25/2008US20080316788 Semiconductor memory device and method for operating semiconductor memory device
12/25/2008US20080316787 Method and apparatus for address allotting and verification in a semiconductor device
12/24/2008EP2006858A2 Micro-tile memory interface
12/24/2008EP2005435A2 Lus semiconductor and application circuit
12/24/2008DE102007028802A1 Integrierte Logikschaltung und Verfahren zum Herstellen einer integrierten Logikschaltung Integrated logic circuit and method of fabricating an integrated logic circuit
12/24/2008DE10058231B4 Datensynchronisationsschaltung und diese enthaltendes Mehrfachbank-Speicherbauelement Data synchronization circuit and these containing multiple bank memory device
12/24/2008DE10036446B4 Vorrichtung zum Erzeugen einer Speicheradresse, Mobilstation und Verfahren zum Schreiben/Lesen von Daten An apparatus for generating a memory address, mobile station and method of writing / reading data
12/24/2008CN101331457A 同步一位接口协议或数据结构 A synchronous interface protocol or data structures
12/24/2008CN101329910A Phase change memory device
12/24/2008CN101329896A Semiconductor storage device having short resetting time
12/24/2008CN100446245C Stacked dram memory chip for a dual inline memory module (dimm)
12/23/2008US7469404 Bank assignment for partitioned register banks
12/23/2008US7468931 Memory device and method for operating a memory device
12/18/2008WO2008130878A3 Techniques for improved timing control of memory devices
12/18/2008US20080310246 Programmable pulsewidth and delay generating circuit for integrated circuits
12/18/2008US20080310242 Systems for programmable chip enable and chip address in semiconductor memory
12/18/2008US20080310229 Semiconductor memory device in which word lines are driven from either side of memory cell array
12/18/2008US20080310218 Semiconductor memory device and its data reading method
12/18/2008US20080309383 Semiconductor Integrated Circuit
12/18/2008US20080309369 Semiconductor integrated circuits with power reduction mechanism
12/18/2008DE102008028035A1 Halbleiterspeichereinrichtung und Verfahren zum Betreiben einer Halbleiterspeichereinrichtung A semiconductor memory device and method of operating a semiconductor memory device
12/18/2008DE10124112B4 Halbleiterspeicher für Hochgeschwindigkeitsbetrieb und Verfahren zum Antreiben einer Wortleitung A semiconductor memory for high speed operation and method of driving a word line
12/17/2008CN100444379C Stacked semiconductor device and semiconductor chip control method
12/16/2008US7467264 Methods and apparatuses for determining the state of a memory element
12/16/2008US7466623 Pseudo SRAM capable of operating in continuous burst mode and method of controlling burst mode operation thereof
12/16/2008US7466622 Method for controlling time point for data output in synchronous memory device
12/16/2008US7466621 Row address controller
12/16/2008US7466620 System and method for low power wordline logic for a memory
12/16/2008US7466619 Semiconductor memory device
12/16/2008US7466609 Semiconductor memory device and semiconductor memory device control method
12/11/2008WO2008150844A1 Memory structure with word line buffers
12/11/2008US20080304354 Semiconductor memory device and method for reading/writing data thereof
12/11/2008US20080304353 Memory storage device with heating element
12/11/2008US20080304352 Memory controllers and pad sequence control methods thereof
12/11/2008US20080304351 Pin Multiplexing
12/11/2008US20080304350 Signal processing circuit
12/11/2008US20080304338 Semiconductor memory device
12/11/2008US20080304334 Synchronous semiconductor memory device having on-die termination circuit and on-die termination method
12/11/2008US20080304332 Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
12/11/2008US20080304331 Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
12/11/2008US20080304321 Serial Flash Memory Device and Precharging Method Thereof
12/10/2008EP1999755A1 Non- volatile semiconductor memory with page erase
12/10/2008EP1714286B1 High voltage driver circuit with fast reading operation
12/10/2008CN101320589A Motherboard and its internal memory apparatus
12/09/2008US7464231 Method for self-timed data ordering for multi-data rate memories
12/09/2008US7463640 Self-synchronous FIFO memory device
12/09/2008US7463548 Method for performing a burn-in test
12/09/2008US7463547 Micro computer and method of optimizing microcomputer
12/09/2008US7463546 Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders
12/09/2008US7463545 System and method for reducing latency in a memory array decoder circuit
12/09/2008US7463544 Device programmable to operate as a multiplexer, demultiplexer, or memory device
12/09/2008US7463536 Memory array incorporating two data busses for memory array block selection
12/09/2008CA2578837C High speed otp sensing scheme
12/04/2008WO2008002581A3 Multi-port memory device and method
12/04/2008WO2007117773A3 Memory with clocked sense amplifier
12/04/2008US20080298159 Semiconductor integrated circuit
12/04/2008US20080298158 Two transistor wordline decoder output driver
12/04/2008US20080298153 Semiconductor memory device
12/04/2008US20080298149 Current reduction with wordline bit line short-circuits in drams and dram derivatives
12/04/2008US20080298144 Semiconductor Memory Device Capable of Confirming a Failed Address and a Method Therefor
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