Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
01/2010
01/21/2010US20100014366 Semiconductor memory devices having signal delay controller and methods performed therein
01/21/2010US20100014365 Data input circuit and nonvolatile memory device including the same
01/21/2010US20100014364 Memory system and method using stacked memory device dice, and system using the memory system
01/21/2010US20100014342 Semiconductor storage device
01/21/2010US20100014341 Semiconductor memory device
01/21/2010DE19928454B4 Speichervorrichtung mit Reihendecodierer Memory device with row decoder
01/21/2010DE19740329B4 Halbleiterspeicherbauelement mit Mehrfachbank Semiconductor memory device having multiple bank
01/21/2010DE10216607B4 Halbleiterspeichervorrichtung A semiconductor memory device
01/20/2010CN100583297C Shift register and image display apparatus containing the same
01/20/2010CN100583287C Addressing circuit for a cross-point memory array including cross-point resistive elements
01/19/2010US7650481 Dynamic control of memory access speed
01/19/2010US7649802 Method for controlling time point for data output in synchronous memory device
01/19/2010US7649801 Semiconductor memory apparatus having column decoder for low power consumption
01/19/2010US7649800 Logic circuit and word-driver circuit
01/19/2010US7649799 Semiconductor memory device
01/19/2010US7649774 Method of controlling memory system
01/19/2010US7649769 Circuit arrays having cells with combinations of transistors and nanotube switching elements
01/14/2010WO2009097677A8 Non-volatile memory device having configurable page size
01/14/2010US20100011266 Program verify method for otp memories
01/14/2010US20100008177 Semiconductor memory device
01/14/2010US20100008176 Write Leveling Of Memory Units Designed To Receive Access Requests In A Sequential Chained Topology
01/14/2010US20100008173 Semiconductor memory device
01/14/2010US20100008171 Read assist circuit of sram with low standby current
01/14/2010US20100008169 Latency Control Circuit and Method Thereof and an Auto-Precharge Control Circuit and Method Thereof
01/14/2010US20100008168 Programmable control block for dual port sram application
01/14/2010US20100008167 Semiconductor memory device and operation method thereof
01/14/2010US20100008157 Semiconductor memory device capable of detecting write completion at high speed
01/14/2010US20100008156 Semiconductor memory device and method for operating the same
01/14/2010US20100008144 System and memory for sequential multi-plane page memory operations
01/14/2010US20100008126 Three-dimensional memory device
01/14/2010DE10361496B4 Anordnung mit einer Speichereinrichtung und einer programmgesteuerten Einheit Arrangement with a memory device and a programmable unit
01/13/2010CN100580812C Nonvolatile semiconductor memory device and data write method thereof
01/13/2010CN100580802C Multi-port memory device with serial input/output interface
01/13/2010CN100580801C Memory chip architecture having non-rectangular memory banks and method for arranging memory banks
01/12/2010US7646688 Disc with temporary disc definition structure (TDDS) and temporary defect list (TDFL), and method of and apparatus for managing defect in the same
01/12/2010US7646668 Maintaining dynamic count of FIFO contents in multiple clock domains
01/12/2010US7646667 Flash EEprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
01/12/2010US7646666 Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
01/12/2010US7646665 Semiconductor memory device and burn-in test method thereof
01/12/2010US7646664 Semiconductor device with three-dimensional array structure
01/12/2010US7646663 Semiconductor memory device and word line addressing method in which neighboring word lines are discontinuously addressed
01/12/2010US7646653 Driver circuits for integrated circuit devices that are operable to reduce gate induced drain leakage (GIDL) current in a transistor and methods of operating the same
01/12/2010US7646629 Method for operating a data storage apparatus employing passive matrix addressing
01/12/2010CA2645774C A power up detection system for a memory device
01/07/2010US20100005391 Access control apparatus, access control method, and access control program
01/07/2010US20100002531 Multi-Port Memory Devices Having Clipping Circuits Therein that Inhibit Data Errors During Overlapping Write and Read Operations
01/07/2010US20100002527 Power up detection system for a memory device
01/07/2010US20100002526 Latch-based Random Access Memory
01/07/2010US20100002525 Array Data Input Latch and Data Clocking Scheme
01/07/2010US20100002503 Integrated Circuits and Methods for Operating the Same Using a Plurality of Buffer Circuits in an Access Operation
01/07/2010US20100002495 Column Selectable Self-Biasing Virtual Voltages for SRAM Write Assist
01/07/2010US20100002490 Electric element, memory device, and semiconductor integrated circuit
01/07/2010US20100001758 Controlling for variable impedance and voltage in a memory system
01/06/2010EP1643356B1 Parallel processing device and parallel processing method
01/06/2010CN100578672C Displacement register
01/06/2010CN100578666C Method and apparatus for implementing high speed memory
01/06/2010CN100578662C Register access device and method
01/05/2010US7644429 Broadcast and reception, and conditional access system therefor
01/05/2010US7643373 Driving method and system for a phase change memory
01/05/2010US7643372 Semiconductor integrated circuit
01/05/2010US7643371 Address/data multiplexed device
01/05/2010US7643370 Memory device having conditioning output data
01/05/2010US7643366 Semiconductor integrated circuit
01/05/2010US7643360 Method and apparatus for synchronization of row and column access operations
01/05/2010US7642601 Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device
12/2009
12/31/2009US20090323457 System and method for synchronizing asynchronous signals without external clock
12/31/2009US20090323456 Multiple device apparatus, systems, and methods
12/31/2009US20090323455 Word line driver, method for driving the word line driver, and semiconductor memory device having the word line driver
12/31/2009US20090323454 Semiconductor memory device
12/31/2009US20090323453 Dynamic Power Saving Memory Architecture
12/31/2009US20090323450 Non-volatile programmable memory cell and memory array
12/31/2009US20090323443 Semiconductor memory device
12/31/2009US20090323442 Semiconductor memory device and reset control circuit of the same
12/31/2009US20090323441 Write Latency Tracking Using a Delay Lock Loop in a Synchronous DRAM
12/31/2009US20090323436 Refresh signal generating circuit
12/31/2009US20090323427 Semiconductor memory device
12/31/2009US20090323423 Methods, circuits and systems for reading non-volatile memory cells
12/31/2009US20090323416 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells
12/31/2009US20090323399 Semiconductor memory device
12/31/2009US20090323398 Semiconductor memory device comprising a plurality of static memory cells
12/31/2009US20090323390 Semiconductor memory device
12/31/2009DE19954564B4 Steuerungsschaltung für die CAS-Verzögerung Control circuit for the CAS latency
12/31/2009DE10165025B4 Halbleiterspeicherbauelement mit Subwortleitungstreibern The semiconductor memory device with Subwortleitungstreibern
12/31/2009DE10130752B4 Halbleiterspeichervorrichtung mit Schaltung zur Erzeugung eines verstärkten Potentials und zugehöriges Steuerverfahren A semiconductor memory device with circuitry for generating a boosted potential and associated control method
12/30/2009WO2009158275A1 Dynamic power saving memory architecture
12/30/2009EP1673782B1 Mram array with segmented word and bit lines
12/30/2009CN100576358C Latched programming of memory and method
12/30/2009CA2726279A1 Dynamic power saving memory architecture
12/29/2009US7640391 Integrated circuit random access memory capable of automatic internal refresh of memory array
12/29/2009US7639561 Multi-port memory device having variable port speeds
12/29/2009US7639560 Output control signal generating circuit
12/29/2009US7639559 Semiconductor memory device
12/29/2009US7639558 Phase change random access memory (PRAM) device
12/29/2009US7639557 Configurable random-access-memory circuitry
12/29/2009US7639549 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
12/24/2009US20090316514 Delay Locked Loop Implementation in a Synchronous Dynamic Random Access Memory
12/24/2009US20090316513 Semiconductor memory apparatus having a sub-word line driver for increasing an area margin in the memory core area
12/24/2009US20090316512 Block redundancy implementation in heirarchical ram's
12/24/2009US20090316510 Semiconductor device and data processing system
12/24/2009US20090316508 PRECISE tRCD MEASUREMENT IN A SEMICONDUCTOR MEMORY DEVICE
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