Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
09/2000
09/27/2000EP1039369A1 Improved skew pointer generation
09/26/2000US6125421 Independent multichannel memory architecture
09/26/2000US6125157 Delay-locked loop circuitry for clock delay adjustment
09/26/2000US6125078 Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system
09/26/2000US6125075 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
09/26/2000US6125072 Method and apparatus for contiguously addressing a memory system having vertically expanded multiple memory arrays
09/26/2000US6125070 Semiconductor memory device having multiple global I/O line pairs
09/26/2000US6125065 Semiconductor memory with column gates and method of controlling column gates during a write mask operation
09/26/2000US6125064 CAS latency control circuit
09/26/2000US6125058 System for optimizing the equalization pulse of a read sense amplifier for a simultaneous operation flash memory device
09/21/2000WO2000055853A1 Portable data storage/audio reproduction apparatus
09/20/2000EP1037212A1 Semiconductor integrated circuit device
09/20/2000CN1267058A Driving apparatus, driving system, and data write-in and/or read-out method
09/19/2000USRE36875 Semiconductor memory device capable of performing test mode operation and method of operating such semiconductor device
09/19/2000US6122718 Column address counter with minus two subtractor for address compare
09/19/2000US6122705 Semiconductor memory device multiplying system clock for storing data different in data length
09/19/2000US6122704 Integrated circuit for identifying an item via a serial port
09/19/2000US6122688 Protocol for communication with dynamic memory
09/19/2000US6122230 Universal compressed audio player
09/19/2000US6122220 Circuits and methods for generating internal signals for integrated circuits by dynamic inversion and resetting
09/19/2000US6122219 Split array semiconductor graphics memory architecture supporting maskable block write operation
09/19/2000US6122217 Multi-bank memory input/output line selection
09/19/2000US6122213 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
09/19/2000US6122212 Sense amplifier with feedbox mechanism
09/19/2000US6122211 Fast, low power, write scheme for memory circuits using pulsed off isolation device
09/19/2000US6122210 Data out buffer circuit and SRAM
09/19/2000US6122204 Sense amplifier having a bias circuit with a reduced size
09/19/2000US6122203 Method, architecture and circuit for writing to and reading from a memory during a single cycle
09/19/2000US6122202 CASB buffer circuit of semiconductor memory device
09/19/2000US6122194 Semiconductor memory device with a column redundancy occupying a less chip area
09/19/2000US6122190 Semiconductor memory device capable of high speed plural parallel test
09/19/2000US6121913 Electronic system with high speed, low power, A/D converter
09/19/2000CA2176984C Capacitive interface for coupling between a music chip and audio player
09/14/2000DE10010497A1 Audio record-replay unit with provision for reproducing images and text, includes system limiting replay of data selected from memory card, by use of counter and comparator
09/13/2000EP1035652A1 Capacitive coupled driver circuit
09/13/2000EP1035548A1 Synchronous semiconductor memory device
09/13/2000EP1034463A1 Method and apparatus for audibly indicating when a predetermined location has been encountered in stored data
09/13/2000CN1266266A Capacitance coupled driving circuit
09/13/2000CN1266265A Latching type read amplifier circuit
09/13/2000CN1266264A Editing device, editing method and recording medium
09/13/2000CN1266263A Method and device for reproducing, method and device for editing
09/12/2000US6119242 Synchronous clock generator including a false lock detector
09/12/2000US6119211 Circuit for controlling writing data into memory and allowing concurrent reset generation and writing data operation
09/12/2000US6119210 Device for the protection of stored data using a time delay circuit
09/12/2000US6119200 System and method to protect SDRAM data during warm resets
09/12/2000US6119181 I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
09/12/2000US6119175 On-chip communication circuit and protocol for microcontroller-based ASICs
09/12/2000US6118869 System and method for PLD bitstream encryption
09/12/2000US6118731 Method of eliminating signal skew in a synchronized dynamic random-access memory device
09/12/2000US6118730 Phase comparator with improved comparison precision and synchronous semiconductor memory device employing the same
09/12/2000US6118729 Synchronous semiconductor memory device
09/12/2000US6118721 Random access memory with divided memory banks and data read/write architecture therefor
09/12/2000US6118718 Semiconductor memory device in which a BIT line pair having a high load is electrically separated from a sense amplifier
09/12/2000US6118717 Method and apparatus for loading directly onto bit lines in a dynamic random access memory
09/12/2000US6118716 Method and apparatus for an address triggered RAM circuit
09/12/2000US6118715 Semiconductor memory device having improved manner of data line connection in hierarchical data line structure
09/12/2000US6118714 Semiconductor memory circuit with bit lines discharging means
09/12/2000US6118711 Apparatus for testing redundant elements in a packaged semiconductor memory device
09/12/2000US6118708 Semiconductor memory device
09/12/2000US6118707 Method of operating a field programmable memory array with a field programmable gate array
09/12/2000US6118694 Distributing CFI devices in existing decoders
09/12/2000US6118333 Clock buffer circuit and clock signal buffering method which can suppress current consumption
09/12/2000US6118323 Electrostatic discharge protection circuit and method
09/12/2000US6118319 Timing signal generation circuit
09/08/2000WO2000052684A1 Recording device, recording method, reproducing device and reproducing method
09/08/2000WO2000052581A1 Data processing device, data processing method, terminal, transmission method for data processing device
09/08/2000WO1999061971A9 Programmable delay timing calibrator for high speed data interface
09/08/2000WO1999021175A3 Integrated circuit layout methods and layout structures
09/07/2000DE19958614A1 Decoding circuit in semiconductor integrated circuit and operational method with selection signal detector
09/07/2000DE19908428A1 Halbleiterspeicheranordnung mit Bitleitungs-Twist A semiconductor memory device with bit line twist
09/07/2000DE10010440A1 Synchronous dynamic memory with random access memory (SDRAM) a process for column access scan (CAS) latency
09/06/2000EP1033721A2 Programmable delay control in a memory
09/06/2000EP1033665A2 Data communication system and data managing method
09/06/2000CN1265746A Optical logic element and methods for respectively its preparation and optical adressing, as well as the use thereof in optical logic device
09/06/2000CN1265510A Dynamic logic circuit
09/06/2000CN1265509A Programmable delay control for use in storage
09/05/2000USRE36851 Method and circuit for shortcircuiting data transfer lines and semiconductor memory device having the circuit
09/05/2000US6115322 Semiconductor device accepting data which includes serial data signals, in synchronization with a data strobe signal
09/05/2000US6115321 Synchronous dynamic random access memory with four-bit data prefetch
09/05/2000US6115319 Dynamic RAM having word line voltage intermittently boosted in synchronism with an external clock signal
09/05/2000US6115318 Clock vernier adjustment
09/05/2000US6115317 Semiconductor memory device for masking data by controlling column select line signals
09/05/2000US6115316 Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type
09/05/2000US6115314 Method and apparatus for anticipatory selection of external or internal addresses in a synchronous memory device
09/05/2000US6115312 Programmable logic device memory cell circuit
09/05/2000US6115311 Semiconductor memory device capable of selecting a plurality of refresh cycle modes
09/05/2000US6115309 Sense amplifier having increased drive current capability
09/05/2000US6115308 Sense amplifier and method of using the same with pipelined read, restore and write operations
09/05/2000US6115307 Method and structure for rapid enablement
09/05/2000US6115306 Method and apparatus for multiple row activation in memory devices
09/05/2000US6115299 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
09/05/2000US6115298 Semiconductor device with automatic impedance adjustment circuit
09/05/2000US6115297 Semiconductor memory circuit with a control circuit rising cell drain potential slowly
09/05/2000US6115295 Efficient back bias (VBB) detection and control scheme for low voltage DRAMS
09/05/2000US6115289 Flash memory device
09/05/2000US6115288 Semiconductor memory device
09/05/2000US6115284 Memory device with faster write operation
09/05/2000US6115282 Dynamic memory
09/05/2000US6115280 Semiconductor memory capable of burst operation
09/05/2000US6115279 System with meshed power and signal buses on cell array